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(unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wDXLzL8O_9p486jAQ--.37610S2; Sat, 09 May 2026 21:51:57 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 0/3] PCI: dwc: Cache PCIe capability offset and simplify drivers Date: Sat, 9 May 2026 21:51:49 +0800 Message-Id: <20260509135152.2241235-1-18255117159@163.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CM-TRANSID: _____wDXLzL8O_9p486jAQ--.37610S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cw1kuFy3ZryfAw4ruFWxWFg_yoW8CF1rpa y5tFWIyF1rtF4avF4Yy3WDuF13t3Z7AFWDK39xW3WSvFyaka1UXr1rtryrtr9rtrWIqr13 Kr1Uta47GF4fJFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziO6pDUUUUU= X-Originating-IP: [140.206.53.66] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwx1oDGn-O-395gAA3x X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260509_065228_434681_79FE4FB8 X-CRM114-Status: UNSURE ( 7.46 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org The DWC PCIe core and its many platform drivers repeatedly call dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the PCI Express Capability structure. This is wasteful and makes the code verbose. And some even search for the PCI_CAP_ID_EXP offset value within the suspend/resume functions. Add a cached pcie_cap field in struct dw_pcie and a helper dw_pcie_get_pcie_cap() to initialize it once at probe time. Then replace all explicit capability searches with the cached value across the entire dwc subtree. Hans Zhang (3): PCI: dwc: Add pcie_cap field and helper in designware header PCI: dwc: Use cached PCIe capability offset in core PCI: dwc: Simplify platform drivers using cached capability offset drivers/pci/controller/dwc/pci-imx6.c | 6 +-- .../pci/controller/dwc/pci-layerscape-ep.c | 4 +- drivers/pci/controller/dwc/pci-meson.c | 4 +- .../pci/controller/dwc/pcie-designware-ep.c | 4 +- .../pci/controller/dwc/pcie-designware-host.c | 4 +- drivers/pci/controller/dwc/pcie-designware.c | 16 +++--- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++ drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++--- drivers/pci/controller/dwc/pcie-eswin.c | 3 +- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 ++-- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++----- drivers/pci/controller/dwc/pcie-sophgo.c | 8 ++- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 5 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-- drivers/pci/controller/dwc/pcie-tegra194.c | 51 +++++++------------ 17 files changed, 85 insertions(+), 97 deletions(-) base-commit: 70390501d1944d4e5b8f7352be180fceb3a44132 -- 2.34.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic