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(unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wDXLzL8O_9p486jAQ--.37610S3; Sat, 09 May 2026 21:51:58 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: mx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/3] PCI: dwc: Add pcie_cap field and helper in designware header Date: Sat, 9 May 2026 21:51:50 +0800 Message-Id: <20260509135152.2241235-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260509135152.2241235-1-18255117159@163.com> References: <20260509135152.2241235-1-18255117159@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDXLzL8O_9p486jAQ--.37610S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7KFWxCF4kArWUWw4fGr1fXrb_yoW8Ww45pa y3JFySkF48AFWava13AanxZr15tas3ArW7Ga9rKw1SqF9xCFyUGa18AryYyF17Kr4Ikrya kw45t34rCFn8JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zE3CzZUUUUU= X-Originating-IP: [140.206.53.66] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxB5oDGn-O-4CewAA3U X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260509_065227_032220_F5CB6D12 X-CRM114-Status: UNSURE ( 9.93 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Add a pcie_cap field to struct dw_pcie to store the offset of the PCI Express Capability structure. Provide a helper dw_pcie_get_pcie_cap() which performs the capability search on first call and caches the result. This is a preparatory step for replacing repetitive capability searches in both core and platform drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 3e69ef60165b..4baf7eb072eb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -568,6 +568,8 @@ struct dw_pcie { * use_parent_dt_ranges to true to avoid this warning. */ bool use_parent_dt_ranges; + + u8 pcie_cap; /* PCIe capability offset */ }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -805,6 +807,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, reg, val); } +/** + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset + * @pci: DWC instance + * + * Finds and caches the offset of PCI_CAP_ID_EXP on first call. + * Returns 0 if the capability is not present. + */ +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci) +{ + if (!pci->pcie_cap) + pci->pcie_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + return pci->pcie_cap; +} + static inline int dw_pcie_start_link(struct dw_pcie *pci) { if (pci->ops && pci->ops->start_link) -- 2.34.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic