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(unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S3; Mon, 20 Jul 2026 23:07:56 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 09/16] PCI: dwc: intel-gw: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:12 +0800 Message-Id: <20260720150619.24733-10-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7GF1xWrW8JrykKFy3Cr1fCrg_yoW8JF17pa y5Xr1jyFn5XF429F17A3Z8XF1Yy3ZxA3s3Ga97Gr1SvF9rCryDK3yqkryFkF9rGFW0vw1a kw1Utw17Grn8JrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pig_-QUUUUU= X-Originating-IP: [240e:b8f:91b3:d000:f138:f837:e143:4264] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AyzV2peOcx2MwAA3A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260720_080818_005082_1C2ECD79 X-CRM114-Status: UNSURE ( 9.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org dw_pcie_host_init() calls .init before caching the offset, so inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (hardware is already enabled). The helper will cache the result for later use. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-intel-gw, the call chain is: static const struct dw_pcie_host_ops intel_pcie_dw_ops = { .init = intel_pcie_rc_init, }; intel_pcie_rc_init() -> intel_pcie_host_setup() -> intel_pcie_link_setup() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index 348e579e683f..a891c3f8eb01 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -119,7 +119,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie *pcie) static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(&pcie->pci); val = pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); -- 2.34.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic