From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Kevin Hilman <khilman@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
Chuan Liu <chuan.liu@amlogic.com>
Subject: [PATCH v2 03/12] soc: amlogic: clk-measure: Support more measurement channels
Date: Sun, 20 Sep 2026 18:25:05 +0800 [thread overview]
Message-ID: <20260920-more-socs-to-support-clk_measure-v2-3-224382a429e8@amlogic.com> (raw)
In-Reply-To: <20260920-more-socs-to-support-clk_measure-v2-0-224382a429e8@amlogic.com>
From: Chuan Liu <chuan.liu@amlogic.com>
On S4 and C3, as well as later SoCs, the clk-measure IP expands the
number of supported measurement channels from 128 to 256. Accordingly,
the MSR_CLK_SRC field in the register is extended from 7 bits to 8 bits.
To support both the old and new implementations, the driver now
uniformly defines the valid MSR_CLK_SRC field as bits[27:20].
For SoCs where MSR_CLK_SRC is only 7 bits wide, the driver never sets
bit27, and on those SoCs bit27 is read-only. Therefore, using
bits[27:20] as the unified field definition does not introduce any
behavioral change or compatibility issue for existing SoCs.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/soc/amlogic/meson-clk-measure.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
index 8a1a9fed0e74..0d4ba2555d17 100644
--- a/drivers/soc/amlogic/meson-clk-measure.c
+++ b/drivers/soc/amlogic/meson-clk-measure.c
@@ -20,7 +20,7 @@ static DEFINE_MUTEX(measure_lock);
#define MSR_CONT BIT(17) /* continuous measurement */
#define MSR_INTR BIT(18) /* interrupts */
#define MSR_RUN BIT(19)
-#define MSR_CLK_SRC GENMASK(26, 20)
+#define MSR_CLK_SRC GENMASK(27, 20)
#define MSR_BUSY BIT(31)
#define MSR_VAL_MASK GENMASK(15, 0)
--
2.42.0
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next prev parent reply other threads:[~2026-09-20 10:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-20 10:25 [PATCH v2 00/12] soc: amlogic: clk-measure: Add support for more SoCs Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 01/12] dt-bindings: soc: amlogic: Reordering compatible of clk-measure Chuan Liu via B4 Relay
2026-09-24 12:56 ` Krzysztof Kozlowski
2026-09-20 10:25 ` [PATCH v2 02/12] dt-bindings: soc: amlogic: Add clk-measure compatible to support more SoCs Chuan Liu via B4 Relay
2026-09-24 12:57 ` Krzysztof Kozlowski
2026-09-20 10:25 ` Chuan Liu via B4 Relay [this message]
2026-09-20 10:25 ` [PATCH v2 04/12] soc: amlogic: clk-measure: Align compatible entries with DT bindings Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 05/12] soc: amlogic: clk-measure: Add support for more SoCs Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 06/12] soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 07/12] arm64: dts: amlogic: a5: Add clk-measure controller node Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 08/12] arm64: dts: amlogic: a4: " Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 09/12] arm64: dts: amlogic: s7: " Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 10/12] arm64: dts: amlogic: s7d: " Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 11/12] arm64: dts: amlogic: s6: " Chuan Liu via B4 Relay
2026-09-20 10:25 ` [PATCH v2 12/12] arm64: dts: amlogic: a9: " Chuan Liu via B4 Relay
2026-09-30 13:22 ` [PATCH v2 00/12] soc: amlogic: clk-measure: Add support for more SoCs Neil Armstrong
2026-10-02 9:27 ` (subset) " Neil Armstrong
2026-10-02 9:28 ` Neil Armstrong
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