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charset="us-ascii"; Format="flowed" Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Krzysztof Sorry for the late reply. As we discussed eariler, I would like to show you how the hardware module canvas work and why it is needed inside the Amlogic's SOCs. Hope this answers your questions. 1. What is canvas? How it works? The architecture is presented in the following diagram: +-----------------------------------+ | Linux Kernel (CPU) | | +---------------------------+ | | | | | | | V4L2 Decoder Driver | | | | | | | +---------------------------+ | +------|----------|---------^-------+ | | | DMA APB IRQ | | | +-------------|----------|---------|------------+ | Hardware | | | | | v v | | | +----------------------------------+ | | | | | | | AMRISC | | | | | | | +----------------------------------+ | | | | | | | Decoder HW | | | | | | | +---|-----|-----|--------|-----|---+ | | idx1 idx2 idx3 ... idx254 idx255 | | | | | | | | | v v v v v | | +----------------------------------+ | | | | | | | Canvas | | | | | | | +---|-----|-----|--------|-----|---+ | +----------|-----|-----|--------|-----|---------+ PA1 PA2 PA3 ... PA254 PA255 | | | | | v v v v v +-----------------------------------------------+ | | | DDR | | | +-----------------------------------------------+ Canvas is a hardware module which maintains an on-chip-memory table. Each table entry describes a physical continuous memory region with its properties such as start address, size and the endian settings. The design of Video decoder hardware uses canvas index to accesses memory. E.g. canvas #10 is configured to start from address 0x10000, size 1MB with little endian. And then this index number #10 is set to a hardware decoder register to set up a buffer destination. Canvas index is basically a reference to a memory region and its configurations. And a single decoder hardware register may take the canvas indexes for all three YUV components, which is helpful for AMRISC' s firmware (assembly coding) when setting up HW decoder configurations. Memory access through canvas has HW out-of-boundary check. And it also has endian controls. 2. Why canvas is needed? 1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we need canvas to prevent the DDR memory used by the decoder from being rewrote by other hardware. Canvas provides the decoder with a configurable DDR memory range, as well as hardware-based detection and blocking for out-of-bounds access. 2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC is the controller of the decoder HW and the decoder driver needs to access the decoder hardware through AMRISC. However, AMRISC is a 16-bit CPU and cannot directly handle 32-bit or 64-bit physical addresses. Therefore, canvas is required to convert the addresses into index to facilitate processing by the AMRISC core. Regards, Zhentao > On 13/02/2026 09:31, Zhentao Guo wrote: >>>>>> + power-domains: >>>>>> + maxItems: 2 >>>>>> + >>>>>> + power-domain-names: >>>>>> + items: >>>>>> + - const: vdec >>>>>> + - const: hevc >>>>>> + >>>>>> + resets: >>>>>> + maxItems: 1 >>>>>> + >>>>>> + amlogic,canvas: >>>>>> + description: should point to a canvas provider node >>>>> Why? What for? >>>>> >>>>> What is canvas provider? >>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c >>> What is this "canvas" device. >> You can think of canvas as the agent through which the decoder hardware >> accesses DDR. > AGAIN: > > What is the canvas device. Describe or point me to bindings describing > it. Your current bindings say that canvas is "a collection of metadata > that describes a pixel buffer" so there is no way it handles DDR access. > > NAK > >>>> In short, canvas is a hardware IP inside the Amlogic SoC. The decoder IP >>>> needs to access DDR through canvas IP, so we need to reference the >>> Why decoder cannot access DDR directly? >> The internal topology of the S4 chip is designed this way, we don't know >> why our VLSI colleauges designed like this. But similar designs have >> been removed in subsequent chips, eliminating the need to rely on a >> common hardware IP. > Quite poor explanation. Based on this, this as well could be entry in > device reg lists. > > Anyway, I am done guessing, explain properly the hardware instead of > answering with half-baked responses just so I will go away. > > > Best regards, > Krzysztof _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic