From: Hans Zhang <18255117159@163.com>
To: sashiko-reviews@lists.linux.dev
Cc: Frank.Li@kernel.org, linux-pci@vger.kernel.org,
imx@lists.linux.dev, neil.armstrong@linaro.org,
linux-amlogic@lists.infradead.org
Subject: Re: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header
Date: Mon, 20 Jul 2026 23:27:29 +0800 [thread overview]
Message-ID: <7b76cdd1-1001-4d2d-a221-33988261faf9@163.com> (raw)
In-Reply-To: <20260720151732.7B9A41F00A3A@smtp.kernel.org>
On 7/20/26 23:17, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] Data race and logically flawed caching in dw_pcie_get_pcie_cap() due to unprotected read-modify-write and failure to cache 'not found' state.
> --
>
> --- Patch [1]: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header ---
> commit ab22dc6f534d77b34df13c99dd929771547f5ff1
> Author: Hans Zhang <18255117159@163.com>
>
> PCI: dwc: Add pcie_cap field and helper in designware header
>
> This commit adds a pcie_cap field to struct dw_pcie to cache the offset of
> the PCI Express Capability structure. It introduces dw_pcie_get_pcie_cap()
> to perform the capability search on the first call and cache the result.
>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
>> --- a/drivers/pci/controller/dwc/pcie-designware.h
>> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> [ ... ]
>> @@ -829,6 +831,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
>> dw_pcie_writel_dbi(pci, reg, val);
>> }
>>
>> +/**
>> + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset
>> + * @pci: DWC instance
>> + *
>> + * Finds and caches the offset of PCI_CAP_ID_EXP on first call.
>> + * Returns 0 if the capability is not present.
>> + */
>> +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci)
>> +{
>> + if (!pci->pcie_cap)
>> + pci->pcie_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>
> [Severity: Medium]
> Will this repeatedly search the configuration space if the capability is
> not found? If dw_pcie_find_capability() returns 0 when the capability is
> missing, pci->pcie_cap will remain 0, causing the search to be repeated
> on every subsequent call instead of being cached.
>
> Also, since this helper might be called concurrently by different threads,
> could the unprotected read and write to pci->pcie_cap cause a data race?
>
Hi,
As mentioned in the previous reply, there is no need for us to worry
about this.
https://lore.kernel.org/linux-pci/5cc6fbcc-98eb-4da5-b123-2c04c4d39326@163.com/
Best regards,
Hans
>> +
>> + return pci->pcie_cap;
>> +}
>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2026-07-20 15:27 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 15:06 [PATCH v3 00/16] PCI: dwc: Cache PCIe capability offset and simplify drivers Hans Zhang
2026-07-20 15:06 ` [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header Hans Zhang
2026-07-20 15:17 ` sashiko-bot
2026-07-20 15:27 ` Hans Zhang [this message]
2026-07-20 15:06 ` [PATCH v3 02/16] PCI: dwc: Use cached PCIe capability offset in core Hans Zhang
2026-07-20 15:28 ` sashiko-bot
2026-08-13 6:06 ` Manivannan Sadhasivam
2026-08-20 15:16 ` Hans Zhang
2026-07-20 15:06 ` [PATCH v3 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Hans Zhang
2026-07-20 15:28 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 04/16] PCI: dwc: layerscape-ep: " Hans Zhang
2026-07-20 15:25 ` sashiko-bot
2026-08-13 18:49 ` Frank Li
2026-07-20 15:06 ` [PATCH v3 05/16] PCI: dwc: meson: " Hans Zhang
2026-07-20 15:17 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 06/16] PCI: dwc: rockchip: " Hans Zhang
2026-07-20 15:21 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 07/16] PCI: dwc: eswin: " Hans Zhang
2026-07-20 15:15 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 08/16] PCI: dwc: fu740: " Hans Zhang
2026-07-20 15:26 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 09/16] PCI: dwc: intel-gw: " Hans Zhang
2026-07-20 15:23 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 10/16] PCI: dwc: qcom-ep: " Hans Zhang
2026-07-20 15:29 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 11/16] PCI: dwc: qcom: " Hans Zhang
2026-07-20 15:19 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 12/16] PCI: dwc: sophgo: " Hans Zhang
2026-07-20 15:20 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 13/16] PCI: dwc: spacemit-k1: " Hans Zhang
2026-07-20 15:19 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 14/16] PCI: dwc: spear13xx: " Hans Zhang
2026-07-20 15:27 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 15/16] PCI: dwc: tegra194: " Hans Zhang
2026-07-20 15:30 ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 16/16] PCI: dwc: ultrarisc: " Hans Zhang
2026-07-20 15:33 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7b76cdd1-1001-4d2d-a221-33988261faf9@163.com \
--to=18255117159@163.com \
--cc=Frank.Li@kernel.org \
--cc=imx@lists.linux.dev \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®