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From: Lucas Tanure <tanure@linux.com>
To: Conor Dooley <conor@kernel.org>
Cc: xianwei.zhao@amlogic.com, Andrew Lunn <andrew+netdev@lunn.ch>,
	 "David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@kernel.org>,
	 Jakub Kicinski <kuba@kernel.org>,
	Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	 Jerome Brunet <jbrunet@baylibre.com>,
	 Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	 Maxime Chevallier <maxime.chevallier@bootlin.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	 Alexandre Torgue <alexandre.torgue@foss.st.com>,
	netdev@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	 linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [RFC PATCH 2/6] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac
Date: Tue, 6 Oct 2026 10:24:32 +0100	[thread overview]
Message-ID: <CAJX_Q+2hD_LTcimHAVhyzgTnp9jYxKKFD2TK5cv9-wLjDh8+wQ@mail.gmail.com> (raw)
In-Reply-To: <asN_-5zalENhkdVA@squawk>

On Mon, Oct 5, 2026 at 11:46 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Oct 04, 2026 at 03:40:42PM +0100, Lucas Tanure wrote:
> > The T7 has the same ethernet glue as the G12A, but the controller
> > reaches DRAM through a pipeline stage that the hardware design inserts
> > in the bus path. That stage has a gate of its own, which no other member
> > of the family has. Nothing else in Linux claims the gate, so it is
> > switched off as unused and the port can then no longer complete a
> > transfer.
> >
> > Describing it means a fourth clock, and the fourth clock of the existing
> > list is the one driving the timing adjustment logic. The T7 applies the
> > RGMII RX delay through PRG_ETH1 and never enables that logic, so it has
> > no use for that clock. Give the T7 a list of its own with the pipeline
> > gate as the fourth entry, under the same name the SD/eMMC controllers of
> > this SoC already use for the equivalent stage on their own bus path. All
> > four entries are required, since the port cannot move data without any
> > of them.
> >
> > The RX delay range is the one the G12A has, since it is the same
> > register field.
> >
> > The compatible pairs the T7 name with the 5.10a Synopsys core the MAC
> > reports, and with the generic fallback.
> >
> > Assisted-by: LLM
> > Signed-off-by: Lucas Tanure <tanure@linux.com>
> > ---
> >  .../bindings/net/amlogic,meson-dwmac.yaml     | 47 +++++++++++++++++++
> >  1 file changed, 47 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > index 90ef79161ab1..96118b4d1560 100644
> > --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
> > @@ -23,6 +23,7 @@ select:
> >            - amlogic,meson-gxbb-dwmac
> >            - amlogic,meson-axg-dwmac
> >            - amlogic,meson-g12a-dwmac
> > +          - amlogic,t7-dwmac
> >    required:
> >      - compatible
> >
> > @@ -57,6 +58,47 @@ allOf:
> >              - const: clkin1
> >              - const: timing-adjustment
> >
> > +  # The T7 applies the RGMII RX delay through PRG_ETH1 and never enables the
> > +  # timing adjustment logic, so it has no timing-adjustment clock. What it does
> > +  # need is the gate of the pipeline stage the controller reaches DRAM through.
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: amlogic,t7-dwmac
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: GMAC main clock
> > +            - description: First parent clock of the internal mux
> > +            - description: Second parent clock of the internal mux
> > +            - description:
> > +                clock of the pipeline stage inserted in the bus path between
> > +                the controller and the DRAM. Without it, the controller cannot
> > +                complete DMA transfers.
>
> Have you checked that this actually works as a limiter to only 4 clocks?
I have now, and it does limit to four. Adding
a fifth clock to the board gets rejected:

  ethernet@fdc00000 (amlogic,t7-dwmac): clock-names:
    ['stmmaceth', 'clkin0', 'clkin1', 'pipeline', 'bogus'] is too long


> There's an additionalItems: true in the snps,dwmac.yaml that I don't
> know if will permit random additional items here.
There are two checks on clocks and both have to pass: snps,dwmac.yaml
allows 1 to 10 items, the t7 branch allows exactly 4. The
additionalItems: true only relaxes the first one, so the second still
rejects a fifth clock. The "exactly 4" is not something I wrote -
dt-schema's _fixup_items_size() sets minItems and maxItems from the
length of the items list.

>
> Cheers,
> Conor.
>
> > +
> > +        clock-names:
> > +          items:
> > +            - const: stmmaceth
> > +            - const: clkin0
> > +            - const: clkin1
> > +            - const: pipeline
> > +
> > +  # Delay definitions for Meson8b and newer (including T7)
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - amlogic,meson8b-dwmac
> > +              - amlogic,meson8m2-dwmac
> > +              - amlogic,meson-gxbb-dwmac
> > +              - amlogic,meson-axg-dwmac
> > +              - amlogic,meson-g12a-dwmac
> > +              - amlogic,t7-dwmac
> > +    then:
> > +      properties:
> >          amlogic,tx-delay-ns:
> >            enum: [0, 2, 4, 6]
> >            default: 2
> > @@ -106,6 +148,7 @@ allOf:
> >            contains:
> >              enum:
> >                - amlogic,meson-g12a-dwmac
> > +              - amlogic,t7-dwmac
> >      then:
> >        properties:
> >          rx-internal-delay-ps:
> > @@ -143,6 +186,10 @@ properties:
> >                - amlogic,meson6-dwmac
> >                - amlogic,meson8m2-dwmac
> >            - const: snps,dwmac
> > +      - items:
> > +          - const: amlogic,t7-dwmac
> > +          - const: snps,dwmac-5.10a
> > +          - const: snps,dwmac
> >
> >    reg:
> >      items:
> > --
> > 2.56.0
> >

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  reply	other threads:[~2026-10-06  9:24 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-04 14:40 [RFC PATCH 0/6] Add ethernet support for the Amlogic T7 Lucas Tanure
2026-10-04 14:40 ` [RFC PATCH 1/6] dt-bindings: net: amlogic,meson-dwmac: spell out the compatible combinations Lucas Tanure
2026-10-05 10:39   ` Conor Dooley
2026-10-04 14:40 ` [RFC PATCH 2/6] dt-bindings: net: amlogic,meson-dwmac: add amlogic,t7-dwmac Lucas Tanure
2026-10-05 10:46   ` Conor Dooley
2026-10-06  9:24     ` Lucas Tanure [this message]
2026-10-04 14:40 ` [RFC PATCH 3/6] net: stmmac: dwmac-meson8b: add support for the Amlogic T7 Lucas Tanure
2026-10-04 15:28   ` Neil Armstrong
2026-10-04 21:13   ` Maxime Chevallier
2026-10-04 14:40 ` [RFC PATCH 4/6] arm64: dts: amlogic: t7: add the ethernet pinctrl nodes Lucas Tanure
2026-10-04 15:28   ` Neil Armstrong
2026-10-04 14:40 ` [RFC PATCH 5/6] arm64: dts: amlogic: t7: add the ethernet controller Lucas Tanure
2026-10-04 15:29   ` Neil Armstrong
2026-10-04 14:40 ` [RFC PATCH 6/6] arm64: dts: amlogic: t7: khadas-vim4: enable the ethernet port Lucas Tanure
2026-10-04 15:29   ` Neil Armstrong
2026-10-04 20:58   ` Maxime Chevallier
2026-10-05 10:04     ` Lucas Tanure
2026-10-05 15:56   ` Andrew Lunn
2026-10-06  9:05     ` Lucas Tanure

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