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From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , Michael Turquette , Stephen Boyd , Brian Masney , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org Subject: [PATCH v2 08/10] clk: bd718x7: Support ROHM BD73800 Message-ID: <032e165ebc5236cb58e91bce7d2e56c64d6a4976.1785838585.git.mazziesaccount@gmail.com> Reply-To: Matti Vaittinen References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="bfzzk+jKxlQKq7Wf" Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT --bfzzk+jKxlQKq7Wf Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable =46rom: Matti Vaittinen The ROHM BD73800 PMIC has a 32.768 kHz clock gate. Add support for controlling this clock. NOTE: The CLKOUT pin can be muxed by an OTP option. On some OTP configurations the CLKOUT is not outputting the clk signal. Signed-off-by: Matti Vaittinen --- Revision history: v1 =3D> : - No changes --- drivers/clk/clk-bd718x7.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c index 1cae974e6d1d..2dc6b8e46f18 100644 --- a/drivers/clk/clk-bd718x7.c +++ b/drivers/clk/clk-bd718x7.c @@ -21,6 +21,9 @@ #define BD718XX_REG_OUT32K 0x2E /* BD72720 */ #define BD72720_REG_OUT32K 0x9a +/* BD73800 */ +#define BD73800_REG_OUT32K 0x50 + /* * BD71837, BD71847, and BD71828 all use bit [0] to clk output control */ @@ -123,6 +126,10 @@ static int bd71837_clk_probe(struct platform_device *p= dev) c->reg =3D BD72720_REG_OUT32K; c->mask =3D CLK_OUT_EN_MASK; break; + case ROHM_CHIP_TYPE_BD73800: + c->reg =3D BD73800_REG_OUT32K; + c->mask =3D CLK_OUT_EN_MASK; + break; default: dev_err(&pdev->dev, "Unknown clk chip\n"); return -EINVAL; @@ -152,6 +159,7 @@ static const struct platform_device_id bd718x7_clk_id[]= =3D { { "bd71828-clk", ROHM_CHIP_TYPE_BD71828 }, { "bd71815-clk", ROHM_CHIP_TYPE_BD71815 }, { "bd72720-clk", ROHM_CHIP_TYPE_BD72720 }, + { "bd73800-clk", ROHM_CHIP_TYPE_BD73800 }, { }, }; MODULE_DEVICE_TABLE(platform, bd718x7_clk_id); --=20 2.55.0 --bfzzk+jKxlQKq7Wf Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmpxvYUACgkQeFA3/03a ocUt6gf/Z79R2a0inH6wCI69ywBpui212rNJBnVRMBPexlrZi758a4NDQgk0YjRI IybHp+0domj40zb8yyizEyPzlYoLejbNPC7e+XSrxW/ut/qNYPeBGsd8S8vWrpg7 4/s8mx/vce2bWuqNXWs8l9xBBBuDGO9trX3eMAkYfghp3X8XNBaS3YIzFX2Nz5Dx ZNJHqfsjW6IaLVNXROQXWcVesWjrvRhfSt7UtArkK5T/eTZpamdLQt5P4VODuAtH 4FhCbzxAw3zsl+yyiIGeXzQKpBxP+8KTs8KvKqLEK+vYLNxkgp3ue5ZT9Aifi93Z 4Ip7EGAb/MjdvOF8e7uf54ImyzQVtA== =as9c -----END PGP SIGNATURE----- --bfzzk+jKxlQKq7Wf--