From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933822AbdDSKtN (ORCPT ); Wed, 19 Apr 2017 06:49:13 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:53560 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761537AbdDSKtK (ORCPT ); Wed, 19 Apr 2017 06:49:10 -0400 Date: Wed, 19 Apr 2017 14:48:56 +0400 From: Razmik Karapetyan Subject: [PATCH 1/3] usb: dwc2: Define PCGCCTL1 register in hw.h To: John Youn , Felipe Balbi , "Greg Kroah-Hartman" , , CC: Razmik Karapetyan MIME-Version: 1.0 Content-Type: text/plain Message-ID: <0bbdaddc-e4f4-4b29-9dfe-d4a21d572ed2@US01WEHTC2.internal.synopsys.com> X-Originating-IP: [10.13.184.19] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCGCCTL1 (Power and Clock Control) register will be used for controlling the core`s active clock gating feature. Signed-off-by: Razmik Karapetyan --- drivers/usb/dwc2/hw.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h index 4592012..b726701 100644 --- a/drivers/usb/dwc2/hw.h +++ b/drivers/usb/dwc2/hw.h @@ -643,6 +643,10 @@ #define PCGCTL_GATEHCLK BIT(1) #define PCGCTL_STOPPCLK BIT(0) +#define PCGCCTL1 HSOTG_REG(0xe04) +#define PCGCCTL1_TIMER (0x3 << 1) +#define PCGCCTL1_GATEEN BIT(0) + #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) /* Host Mode Registers */ -- 2.7.4