Re: [PATCH v5 4/6] reset: anlogic: add support for Anlogic DR1V90 resets

[Philipp Zabel <p.zabel@pengutronix.de>]

Hi Brian,

On Mo, 2026-06-29 at 16:58 -0400, Brian Masney wrote:
> Hi Philipp,
> 
> On Thu, May 14, 2026 at 05:27:20PM +0800, Junhui Liu wrote:
> > Add reset controller support for the Anlogic DR1V90 SoC, which is an
> > auxiliary device associated with the Clock and Reset Unit (CRU). All
> > resets are active-low.
> > 
> > Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> 
> I don't see a Reviewed-by or Acked-by for you on the reset portion of
> this driver.
> 
> I'm gathering a pull for Stephen for various clk drivers that were
> missed during the last merge window. Does all of this usually go in via
> one tree?

When both clk and reset drivers depend on the dt-bindings + headers
patch, often all of it is merged through the clk tree. For this,

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>

> Or Stephen merges the clk part, you merge the reset portion?
> Who usually merges the dts changes?

In most cases clk is the platform device, and reset is just an
auxiliary device. So if I can merge the reset driver on its own, dts
usually goes with clk.

regards
Philipp