mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Vasant Hegde <vasant.hegde@amd.com>,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	joro@8bytes.org, jgg@nvidia.com
Cc: yi.l.liu@intel.com, kevin.tian@intel.com, nicolinc@nvidia.com,
	jon.grimm@amd.com, santosh.shukla@amd.com, Sairaj.K@amd.com,
	jay.chen@amd.com, wvw@google.com, wnliu@google.com,
	dantuluris@google.com, chriscli@google.com, kpsingh@google.com,
	alejandro.j.jimenez@oracle.com, joao.m.martins@oracle.com
Subject: Re: [PATCH 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs
Date: Wed, 2 Sep 2026 19:16:41 +0700	[thread overview]
Message-ID: <0f8c3b25-feb3-4a6c-b258-1e8a66ed238f@amd.com> (raw)
In-Reply-To: <4a7d6c45-0fa9-43f9-b2f5-414449ce0dfd@amd.com>



On 8/10/2026 5:00 PM, Vasant Hegde wrote:
> Hi Suravee,
> 
>> .....
>>
>> diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c
>> index f4b5f96d4785..014ae16bf58b 100644
>> --- a/drivers/iommu/amd/viommu.c
>> +++ b/drivers/iommu/amd/viommu.c
>> @@ -7,9 +7,15 @@
>>   #define dev_fmt(fmt)    pr_fmt(fmt)
>>   
>>   #include <linux/iommu.h>
>> +#include <linux/amd-iommu.h>
>> +
>> +#include <linux/fs.h>
>> +#include <linux/cdev.h>
>> +#include <linux/ioctl.h>
>>   #include <linux/iommufd.h>
>>   #include <linux/amd-iommu.h>
>>   #include <uapi/linux/iommufd.h>
>> +#include <linux/mem_encrypt.h>
>>   
>>   #include <asm/iommu.h>
>>   #include <asm/set_memory.h>
>> @@ -18,12 +24,130 @@
>>   #include "amd_iommu.h"
>>   #include "amd_iommu_types.h"
>>   #include "amd_viommu.h"
>> +#include "../iommu-pages.h"
>> +
>> +LIST_HEAD(viommu_devid_map);
>> +
>> +static int viommu_init_pci_vsc(struct amd_iommu *iommu)
> 
> May be viommu_find_pci_vsc as its not initializing, instead find the offset.

I'll remove this

> Also if we pass vsc_offset to viommu_vf_vfcntl_init() -OR- call this function
> from viommu_vf_vfcntl_init() then we can skip tracking `vsc_offset` in amd_iommu
> structure.

Ok. I'll refactor to consolidate viommu_init_pci_vsc() and 
viommu_vf_vfcntl_init() and remove vsc_offset.

>> +{
>> +	iommu->vsc_offset = pci_find_capability(iommu->dev, PCI_CAP_ID_VNDR);
>> +	if (!iommu->vsc_offset)
>> +		return -ENODEV;
>> +
>> +	DUMP_printk("device:%s, vsc offset:%04x\n",
>> +		    pci_name(iommu->dev), iommu->vsc_offset);
>> +	return 0;
>> +}
>> +
>> +static void amd_viommu_gid_ida_init(struct amd_iommu *iommu)
>> +{
>> +	ida_init(&iommu->gid_ida);
>> +	iommu->gid_ida_inited = true;
> 
> Once we remove `gid_ida_inited` may be we can call `ida_init` inside
> amd_viommu_init() itself.

Ok.

>> +}
>> +
>> +static void amd_viommu_gid_ida_fini(struct amd_iommu *iommu)
>> +{
>> +	if (!iommu->gid_ida_inited)
>> +		return;
>> +
>> +	ida_destroy(&iommu->gid_ida);
>> +	iommu->gid_ida_inited = false;
>> +}
>> +
>> +static void __init amd_viommu_vf_vfcntl_unmap(struct amd_iommu *iommu)
>> +{
>> +	if (iommu->vfctrl_base) {
>> +		iounmap(iommu->vfctrl_base);
>> +		iommu->vfctrl_base = NULL;
>> +	}
>> +	if (iommu->vf_cntl_phys)
>> +		release_mem_region(iommu->vf_cntl_phys, VIOMMU_VF_CNTL_MMIO_MAP_SIZE);
>> +
>> +	if (iommu->vf_base) {
>> +		iounmap(iommu->vf_base);
>> +		iommu->vf_base = NULL;
>> +	}
>> +	if (iommu->vf_base_phys)
>> +		release_mem_region(iommu->vf_base_phys, VIOMMU_VF_MMIO_MAP_SIZE);
>> +}
>> +
>> +void __init amd_viommu_uninit(struct amd_iommu *iommu)
>> +{
>> +	amd_viommu_gid_ida_fini(iommu);
>> +	amd_viommu_vf_vfcntl_unmap(iommu);
>> +}
>> +
>> +static int __init viommu_vf_vfcntl_init(struct amd_iommu *iommu)
>> +{
>> +	u32 lo, hi;
>> +	u64 vf_phys, vf_cntl_phys;
>> +
>> +	/* Setting up VF and VF_CNTL MMIOs */
>> +	pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_LO_OFFSET, &lo);
>> +	pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_HI_OFFSET, &hi);
>> +	vf_phys = hi;
>> +	vf_phys = (vf_phys << 32) | lo;
>> +	if (!(vf_phys & 1)) {
>> +		pr_err(FW_BUG "vf_phys disabled\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BAR_LO_OFFSET, &lo);
>> +	pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BAR_HI_OFFSET, &hi);
>> +	vf_cntl_phys = hi;
>> +	vf_cntl_phys = (vf_cntl_phys << 32) | lo;
>> +	if (!(vf_cntl_phys & 1)) {
>> +		pr_err(FW_BUG "vf_cntl_phys disabled\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	if (!vf_phys || !vf_cntl_phys) {
>> +		pr_err(FW_BUG "AMD-Vi: Unassigned VF resources.\n");
>> +		return -ENOMEM;
>> +	}
> 
> Redundant check as previous check confirms both vf_phys and vf_cntl_phys is
> enabled. If we want to check non-zero address then we have to remove bit zero
> and add check

Good point. I'll remove this for now.

>> +
>> +	/* Mapping 256MB of VF and 4MB of VF_CNTL BARs */
>> +	vf_phys &= ~1ULL;
>> +	iommu->vf_base = iommu_map_mmio_space(vf_phys, VIOMMU_VF_MMIO_MAP_SIZE);
>> +	if (!iommu->vf_base) {
>> +		pr_err("Can't reserve vf_base\n");
>> +		return -ENOMEM;
>> +	}
>> +	iommu->vf_base_phys = vf_phys;
>> +
>> +	vf_cntl_phys &= ~1ULL;
>> +	iommu->vfctrl_base = iommu_map_mmio_space(vf_cntl_phys, VIOMMU_VF_CNTL_MMIO_MAP_SIZE);
>> +	if (!iommu->vfctrl_base) {
>> +		pr_err("Can't reserve vfctrl_base\n");
>> +		goto err_out;
>> +	}
>> +	iommu->vf_cntl_phys = vf_cntl_phys;
>> +
>> +	pr_debug("%s: IOMMU device:%s, vf_base:%#llx, vfctrl_base:%#llx\n",
> 
> better DUMP_printk ?

Actually, I prefer pr_debug().

>> +		 __func__, pci_name(iommu->dev), vf_phys, vf_cntl_phys);
>> +	return 0;
>> +err_out:
>> +	amd_viommu_uninit(iommu);
> 
> Its odd. We shouldn't call amd_viommu_uninit from here. May be call
> amd_viommu_vf_vfcntl_unmap() ?

I'm fixing this in V5.

Thanks,
Suravee

  reply	other threads:[~2026-09-02 12:17 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-27 13:28 [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 01/24] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2026-08-05 17:01   ` Vasant Hegde
2026-09-01  7:56     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 02/24] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-08-10  7:12   ` Vasant Hegde
2026-09-01  8:28     ` Suthikulpanit, Suravee
2026-08-19  8:17   ` guanghuifeng
2026-09-01 14:21     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 03/24] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-08-10  8:13   ` Vasant Hegde
2026-09-01 16:32     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:28 ` [PATCH 05/24] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-08-10  9:21   ` Vasant Hegde
2026-09-02  7:49     ` Suthikulpanit, Suravee
2026-08-24 17:24   ` Jason Gunthorpe
2026-09-02  7:50     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-08-10 10:00   ` Vasant Hegde
2026-09-02 12:16     ` Suthikulpanit, Suravee [this message]
2026-08-19 13:18   ` guanghuifeng
2026-09-02 12:16     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 07/24] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-08-10 10:49   ` Vasant Hegde
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:28 ` [PATCH 08/24] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-08-19  8:34   ` guanghuifeng
2026-09-02 22:33     ` Suthikulpanit, Suravee
2026-07-27 13:28 ` [PATCH 09/24] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:28 ` [PATCH 10/24] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-08-10 11:07   ` Vasant Hegde
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:29 ` [PATCH 11/24] iommu/amd: Export amd_iommu_alloc_dev_data() helper Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:29 ` [PATCH 12/24] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:29 ` [PATCH 13/24] iommu/amd: Assign IOMMU Private Address domain to IOMMU Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-09-08  6:57     ` Suthikulpanit, Suravee
2026-07-27 13:29 ` [PATCH 14/24] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:29 ` [PATCH 15/24] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-08-19 13:30   ` guanghuifeng
2026-09-03  0:41     ` Suthikulpanit, Suravee
2026-07-27 13:29 ` [PATCH 16/24] iommu/amd: Introduce IOMMUFD vDevice support for AMD Suravee Suthikulpanit
2026-08-19 13:34   ` guanghuifeng
2026-09-03  2:41     ` Suthikulpanit, Suravee
2026-08-24 17:24   ` Jason Gunthorpe
2026-07-27 13:29 ` [PATCH 17/24] iommu/amd: Introduce helper function for updating domain ID mapping table Suravee Suthikulpanit
2026-08-19 10:45   ` guanghuifeng
2026-09-03  3:26     ` Suthikulpanit, Suravee
2026-07-27 13:29 ` [PATCH 18/24] iommu/amd: Introduce helper function for updating device " Suravee Suthikulpanit
2026-08-10 15:17   ` Vasant Hegde
2026-09-03  3:19     ` Suthikulpanit, Suravee
2026-08-19 10:26   ` guanghuifeng
2026-09-08  9:40     ` Suthikulpanit, Suravee
2026-07-27 13:29 ` [PATCH 19/24] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 20/24] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 21/24] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 22/24] iommu/amd: Add translate-device-id alloc/free with vIOMMU owner Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 23/24] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-08-19 10:18   ` guanghuifeng
2026-09-08 11:42     ` Suthikulpanit, Suravee
2026-07-27 13:29 ` [PATCH 24/24] iommu/amd: Relocate vIOMMU translate-device-id on PCI reserve Suravee Suthikulpanit
2026-08-19  9:42   ` guanghuifeng
2026-09-03  3:56     ` Suthikulpanit, Suravee
2026-08-11  7:18 ` [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Tian, Kevin
2026-08-24 17:24 ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=0f8c3b25-feb3-4a6c-b258-1e8a66ed238f@amd.com \
    --to=suravee.suthikulpanit@amd.com \
    --cc=Sairaj.K@amd.com \
    --cc=alejandro.j.jimenez@oracle.com \
    --cc=chriscli@google.com \
    --cc=dantuluris@google.com \
    --cc=iommu@lists.linux.dev \
    --cc=jay.chen@amd.com \
    --cc=jgg@nvidia.com \
    --cc=joao.m.martins@oracle.com \
    --cc=jon.grimm@amd.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=kpsingh@google.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=nicolinc@nvidia.com \
    --cc=santosh.shukla@amd.com \
    --cc=vasant.hegde@amd.com \
    --cc=wnliu@google.com \
    --cc=wvw@google.com \
    --cc=yi.l.liu@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®