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[174.112.193.187]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ffb75d7916sm566541cf.7.2026.01.06.17.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 17:13:37 -0800 (PST) Message-ID: <144a39f2d19af30961498acc11d6b7475166ccf5.camel@redhat.com> Subject: Re: [tip: irq/msi] PCI: dwc: Enable MSI affinity support From: Radu Rendec To: Jon Hunter , linux-kernel@vger.kernel.org, linux-tip-commits@vger.kernel.org Cc: Thomas Gleixner , x86@kernel.org, "linux-tegra@vger.kernel.org" Date: Tue, 06 Jan 2026 20:13:36 -0500 In-Reply-To: <9ec6928cd4e7a599d4bbb6ac0258da8997518d3a.camel@redhat.com> References: <20251128212055.1409093-4-rrendec@redhat.com> <176583448396.510.10427292538118156779.tip-bot2@tip-bot2> <44509520-f29b-4b8a-8986-5eae3e022eb7@nvidia.com> <9ec6928cd4e7a599d4bbb6ac0258da8997518d3a.camel@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Jon, On Tue, 2026-01-06 at 10:07 -0500, Radu Rendec wrote: > On Tue, 2026-01-06 at 09:53 +0000, Jon Hunter wrote: > > On 15/12/2025 21:34, tip-bot2 for Radu Rendec wrote: > > > The following commit has been merged into the irq/msi branch of tip: > > >=20 > > > Commit-ID:=C2=A0=C2=A0=C2=A0=C2=A0 eaf290c404f7c39f23292e9ce83b8b5b51= ab598a > > > Gitweb:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 https://git.kernel.= org/tip/eaf290c404f7c39f23292e9ce83b8b5b51ab598a > > > Author:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Radu Rendec > > > AuthorDate:=C2=A0=C2=A0=C2=A0 Fri, 28 Nov 2025 16:20:55 -05:00 > > > Committer:=C2=A0=C2=A0=C2=A0=C2=A0 Thomas Gleixner > > > CommitterDate: Mon, 15 Dec 2025 22:30:48 +01:00 > > >=20 > > > PCI: dwc: Enable MSI affinity support > > >=20 > > > Leverage the interrupt redirection infrastructure to enable CPU affin= ity > > > support for MSI interrupts. Since the parent interrupt affinity canno= t > > > be changed, affinity control for the child interrupt (MSI) is achieve= d > > > by redirecting the handler to run in IRQ work context on the target C= PU. > > >=20 > > > This patch was originally prepared by Thomas Gleixner (see Link tag b= elow) > > > in a patch series that was never submitted as is, and only parts of t= hat > > > series have made it upstream so far. > > >=20 > > > Originally-by: Thomas Gleixner > > > Signed-off-by: Radu Rendec > > > Signed-off-by: Thomas Gleixner > > > Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ > > > Link: https://patch.msgid.link/20251128212055.1409093-4-rrendec@redha= t.com > >=20 > >=20 > > With next-20260105 I am observing the following warning on the Tegra194= =20 > > Jetson AGX platform ... > >=20 > > =C2=A0 WARNING KERN genirq: irq_chip DW-PCI-MSI-0001:01:00.0 did not up= date > > =C2=A0=C2=A0 eff. affinity mask of irq 171 > >=20 > > Bisect is point to this commit. This platform is using the driver=20 > > drivers/pci/controller/dwc/pcie-tegra194.c. Is there some default=20 > > affinity that we should be setting to avoid this warning? >=20 > Before that patch, affinity control wasn't even possible for PCI MSIs > exposed by the dw_pci drivers. Without having looked at the code yet, > I suspect it's just because now that affinity control is enabled, > something tries to use it. >=20 > I don't think you should set some default affinity. By default, the PCI > MSIs should be affine to all available CPUs, and that warning shouldn't > happen in the first place. Let me test on Jetson AGX and see what's > going on. I'll update the thread with my findings, hopefully later > today. I looked at the code and tested, and the problem is that the effective affinity mask is not updated for interrupt redirection. The bug is not in this patch, but the previous one in the series [1], which adds the interrupt redirection framework. The warning is actually triggered when the MSI is set up. This is the top part of the relevant stack trace: irq_do_set_affinity+0x28c/0x300 (P) irq_setup_affinity+0x130/0x208 irq_startup+0x118/0x170 __setup_irq+0x5b0/0x6a0 request_threaded_irq+0xb8/0x180 devm_request_threaded_irq+0x88/0x150 rtw_pci_probe+0x1e8/0x370 [rtw88_pci] I don't immediately see an easy way to fix it for the generic case because the affinity of the=C2=A0demultiplexing IRQ (the "parent" IRQ) can change after the affinity of the demultiplexed IRQ (the "child" IRQ) has been set up. But since dw_pcie is currently the only user of the interrupt redirection infrastructure, and it sets up the demultiplexing IRQ as a chained IRQ, there is no way its affinity can change other than CPU hot(un)plug. And in this particular case, something as simple as will work: diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index d5c3f6ee24cc2..036641f9534ae 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1512,8 +1512,11 @@ EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent)= ; int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpu= mask *dest, bool force) { struct irq_redirect *redir =3D &irq_data_to_desc(data)->redirect; + unsigned int target_cpu =3D cpumask_first(dest); + + WRITE_ONCE(redir->target_cpu, target_cpu); + irq_data_update_effective_affinity(data, cpumask_of(target_cpu)); =20 - WRITE_ONCE(redir->target_cpu, cpumask_first(dest)); return IRQ_SET_MASK_OK; } EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); I will send this as a proper patch tomorrow, and it will fix the immediate problem and buy some time for a more elaborate fix for the generic case. Meanwhile, thanks a lot for finding/reporting this! [1] https://lore.kernel.org/all/20251128212055.1409093-2-rrendec@redhat.com= / --=20 Best regards, Radu