Re: (subset) [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform

[Vinod Koul <vkoul@kernel.org>]

On Mon, 21 Sep 2026 11:07:08 +0530, Krishna Chaitanya Chundru wrote:
> This series adds PCIe support for the Qualcomm Nord (SA8797P) platform.
> 
> Nord has a single Gen5-capable QMP PCIe PHY block split into four
> independently-clocked and independently-resettable ports (A/B/C/D).
> Firmware selects the active lane topology at boot via a TCSR
> configuration register, and the same PHY block can appear as a single
> x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This
> is similar in spirit to the Glymur multi-PHY support already posted,
> except Nord's PHY registers are programmed by Linux rather than by
> firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init
> tables along with the power-up/power-down/soft-reset sequencing needed
> to bring each port up.
> 
> [...]

Applied, thanks!

[1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
      commit: 1a60038589285eec5b345f1da05ba04a185b8db5
[4/6] phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header
      commit: 63cfcae23b2b4ca43994d507f5f04cba0306dd5a
[5/6] phy: qcom: qmp-pcie: Refactor common multiphy handling
      commit: 6dd77bf6a10d0eb9ed17f5b6093b3511052084db
[6/6] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support
      commit: e397c8507e362a29ecfb4aef38b408f2de731526

Best regards,
-- 
~Vinod