From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696713F6C3D for ; Tue, 19 May 2026 09:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181323; cv=none; b=lUwbmJik3YVnWUlnt9OynRbGNE1jZhGXt/1x+OU/wsa8+T1+32MLkPXDBQEwIVlSE/RV+aYA6XcvYVIQ6tvEOhBu3TFtVWAFclbFnUKM7GT8GYHtAsAPXm9+jX3ltd/WnhHy8um6bLUHVMRW8vZ2uuz6fFMWGWKAD6I96d897UQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181323; c=relaxed/simple; bh=bVqS1Abfd3XhxVTJJMr1uiuME/oE+EUAC30jYZW157c=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ZzSnaFwJjpa+tcbIj9kFO5dmmVSw0HlLnS6lbPa6F8vHI/+RIV35IP1qFTjUzoAjgE6j7+wtmGFmNYepRoCja9F9p7Rz4nlRD5qoyqCIs6p0XzmRn5mD4bCgDORRSbDJPNxhmkwillWCqs6HONRyiW0woqmoGgXtCSjuhzUQH4M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ya2wHT1f; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ya2wHT1f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779181322; x=1810717322; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bVqS1Abfd3XhxVTJJMr1uiuME/oE+EUAC30jYZW157c=; b=ya2wHT1fLcujV+t5WXTsHyZnthJCUcnBYZDjeBmTfPNY67CWTXVfNRux UCrqEUuA3kiFaXc0JV9lWQNqCaIJdyNpR2scRHcl48TIc9wbr0BoFLuHD KNwAwsFa1F7Sr6FOLuwwlccAq6Ktiu3ejuhZ9TiKWegomGvaoji/VIcnQ 1+OA/cKI3L1LkFiDRqCy6fPbZl0y0aFk63Ll/TM7AhilepHM9RVYvWJ6l fas2dAOw3X9xVKy+y/zhvq1Y/zbdGSW6D0U7xSMR7k8VZCDGLGy4FCFEJ bSY76kFmyACk+kxjySgvgNUl/cL4IKIziCoa8sJ1dmWI0zBhvmvdSpF8d g==; X-CSE-ConnectionGUID: ax/201G4TeWRIhxu7tRlag== X-CSE-MsgGUID: Sj3WJHEnQjSuGAIDTdsJ8Q== X-IronPort-AV: E=Sophos;i="6.23,243,1770620400"; d="scan'208";a="289088331" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 May 2026 02:01:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 19 May 2026 02:01:55 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 19 May 2026 02:01:51 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: Subject: [PATCH 0/8] drm: atmel-hlcdc: fix clock handling and add LVDS support Date: Tue, 19 May 2026 14:31:27 +0530 Message-ID: <20260519090135.1188405-1-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This series fixes several issues in the atmel-hlcdc CRTC clock handling and adds LVDS display support for XLCDC-based SoCs. The first patch fixes a pre-existing off-by-one error in the vertical back porch register calculation. The following patches progressively clean up the clock divider logic by introducing DIV_ROUND_CLOSEST, defining a named maximum divider constant, and extracting clock setup into a dedicated helper. Clock bypass support is then added for XLCDC hardware when the computed divider is less than 2. The final two patches introduce LVDS PLL clock support, configuring the PLL to 7x the pixel clock rate before the timing engine is programmed, and add an LVDS output mode handler to map LVDS bus formats to the appropriate display output modes. Manikandan Muralidharan (7): drm: atmel-hlcdc: Fix off-by-one in vertical back porch setting drm: atmel-hlcdc: simplify clock divider selection with DIV_ROUND_CLOSEST drm: atmel-hlcdc: define ATMEL_HLCDC_CLKDIV_MAX and fix divider fallback drm: atmel-hlcdc: extract clock setup into a dedicated helper drm: atmel-hlcdc: add XLCDC clock bypass support for small dividers drm: atmel-hlcdc: add and configure LVDS PLL clock support drm: atmel-hlcdc: add LVDS output mode support Ryan Wanner (1): drm: atmel-hlcdc: reorder timing register writes after clock setup .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 190 +++++++++++++----- include/linux/mfd/atmel-hlcdc.h | 2 + 2 files changed, 139 insertions(+), 53 deletions(-) -- 2.25.1