From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 524F8450902 for ; Tue, 19 May 2026 09:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181350; cv=none; b=g0MAZbJ/ct3QCr7gt31HS51YqqE6G5xjGnrdiab6juZ92JvhHE675v3pc6sbI/4KFbRpYb9NtOpeCvsZ1ctusAxPQbyTmds1b59m2nHv909z/atG77OUoYGnC9iWSP2gIUVS+8QgMYNrn3yvTmJpZXn56/upXVHSIFz5cS6QbzU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779181350; c=relaxed/simple; bh=jMsgCKlmkEe87bVAn7RqMCuhljgwv9IJFsxQpoWrUvM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nYYF+39UO07c+IDs4y6BYuHQseEQztcX+PDBEwd9TJw5DhbxEPrgN0T7OCMMxxr44rEn7FU3k6sFaCBwbskih1aI0WFEq/jHr9zm41Bc6kVToNuGcbzSm3pZXYJlIMW5Gwsd/teLS6P1hTOEY8Qz59EwIoJb/HvPHHR4gsgXxZk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=cK8d3Zun; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="cK8d3Zun" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1779181349; x=1810717349; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jMsgCKlmkEe87bVAn7RqMCuhljgwv9IJFsxQpoWrUvM=; b=cK8d3ZunaZJpAWyGQ/6GKa+HFkcWgr6e9sRYdfTpie4+ZzQA0F6a1y0G /gu3ZH1pJQZwGeHQzx9trYtx67jbK3HYy/wAi3rmQWkdZLEFm/CB8tvBW L3UKxpsE+Z0uKDa2gqS675o8xmzck9dG24juLPgC2Ndw2WFrAJTL3HxvY bcOObpOiX541IiDcKQrFRO98YmxtpFqju9KPU/uTuVLGg4Fl5vd/00Kzd IqrZygLTk5qOOYBpVnk72XFxB1gl+H+by1wEPZ5QUTLkgICMxLSTQlZOM D/bJ4Yj78krTpIm+lA8Bap8s9fuVXQWHCG+MbfuuMzCcALX/bc4GqDm6J Q==; X-CSE-ConnectionGUID: UhwUzNcxQYenxhztrBU4xA== X-CSE-MsgGUID: sBXINErWS3GRAFZWhBEO9Q== X-IronPort-AV: E=Sophos;i="6.23,243,1770620400"; d="scan'208";a="289088359" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 May 2026 02:02:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 19 May 2026 02:02:28 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 19 May 2026 02:02:23 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: Subject: [PATCH 6/8] drm: atmel-hlcdc: add XLCDC clock bypass support for small dividers Date: Tue, 19 May 2026 14:31:33 +0530 Message-ID: <20260519090135.1188405-7-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260519090135.1188405-1-manikandan.m@microchip.com> References: <20260519090135.1188405-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Define ATMEL_XLCDC_CLKBYP and set the clock bypass bit on XLCDC hardware when the computed divider is less than 2, avoiding an invalid divider value. Non-XLCDC hardware retains the existing minimum divider clamp of 2. Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 +++++++ include/linux/mfd/atmel-hlcdc.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 6da428361c19..f837684654ea 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -87,6 +87,13 @@ static int atmel_hlcdc_crtc_setup_clock(struct atmel_hlcdc_crtc *crtc, div = DIV_ROUND_CLOSEST(prate, mode_rate); if (div < 2) { + /* XLCDC: bypass divider when div < 2 */ + if (crtc->dc->desc->is_xlcdc) { + *cfg |= ATMEL_XLCDC_CLKBYP; + *mask |= ATMEL_XLCDC_CLKBYP; + return 0; + } + /* Enforce minimum divider for non-XLCDC */ div = 2; } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { /* The divider ended up too big, try a lower base rate. */ diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index 8e86219293b7..1463c7db0e64 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -44,6 +44,7 @@ #define ATMEL_XLCDC_HEO_UPDATE BIT(3) #define ATMEL_HLCDC_CLKPOL BIT(0) +#define ATMEL_XLCDC_CLKBYP BIT(1) #define ATMEL_HLCDC_CLKSEL BIT(2) #define ATMEL_HLCDC_CLKPWMSEL BIT(3) #define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i)) -- 2.25.1