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Tue, 25 Aug 2026 14:24:23 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Subject: [PATCH v11 00/12] ZTE zx297520v3 clock bindings and driver Date: Wed, 26 Aug 2026 00:23:59 +0300 Message-Id: <20260826-zx29clk-v11-0-f8ad59c6426c@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/2XRzU7DMAwH8FeZeqbIdr5sTrwH4tAmDlQwBu2YB tPenWwcEsoxVn7/2PGpW3SedOnuNqdu1sO0TLu3ckC82XTxeXh70n5KpdARkAeH0H8fSeLrS09 qkxE1SBy7cvt91jwdr1EPj7/nWT8+S+L+t9iNw6J93G230/5uM7AFrz7CGMREhcAMKJ4NmxAts HOjcyKuu2Q9T8t+N39duzzgNexfPwfsoVcch5hzVvHh/mk7TK+35cFrxoFah9VRcSQZNEUDkN3 amcaRVGeKiyGrszoY5rx2tjqPvjp7cYOIHRORSlo71zji6lxxQXIGa9Wi0Nr56gJQdb44E8IYw GaGaNcuNA5DdaG4sgiLGHPMxq8dN44ax5c+B4Qwlt/E9G8+qY7bPqW4BM4ZSOwS8dohNPDP4qF Ib9h6K2UEiq08n88/ISz1guUCAAA= X-Change-ID: 20260510-zx29clk-2e4d39e3128c To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones , Brian Masney , Jerome Brunet , Manivannan Sadhasivam Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 Hi, I am sending version 11 of my zx297520v3 clock patch. It addresses review comments for the MFD driver but has no other substantial changes I think the list of clocks in my driver is fairly complete; It is certainly a lot better than what the downstream ZTE drivers have. I deduced a lot of it by trial and error. I am sure there are some clocks missing that will need to be added to the binding later. AFAIU adding clocks is not an issue, but removing or reordering them is an ABI break. Merge dependencies: The binding patches (1, 2, 3) and DT patch (4) in order. The MFD parent (5) is independent, although changing the ordering likely needs trivial adjustments in MAINTAINERS. The clock driver patches depend on the headers added by 1-3 and apply in order (6-11). Reset needs headers (1-3), but it is independent of clock. Signed-off-by: Stefan Dösinger --- Changes in v11: Addresses Lee Jones's comments on the MFD patch Reorder the DTSI patch ahead of the driver patch to give it more visibility - it is the only patch in the series that hasn't seen a review so far. It is also order independent of the driver patches. What's the next step after all the individual patches are reviewed? Should I submit them as pull requests to the DT, mfd, clock, reset trees? Or do the maintainers pick them from the list? Changes in v10: *) Clock infrastructure: Fix issues pointed out by Brian. The individual patches have more details in the changelog *) MFD infrastructure: Remove _MFD_ from the match data enums *) Further refinement of LTE related clocks and resets: The ZSP rproc has two resets, one in topcrm and one in matrixcrm. I don't know what the difference between them is, but both need to be deasserted for it to work. Previously I thought the matrixcrm register 0x3c is a clock. The clock gate is actually in 0x34. Changes in v9: *) Use parent_data in the clock driver instead of parent_names. That required some infrastructure to keep track of registered clocks rather than devm-and-forget. A nice side effect is that it uncovered a missing top->matrix clock link. (Brian) *) Remove the self-referencing USB PHY reset in topcrm (Krzysztof) *) (Hopefully) get unevaluatedProperties and additionalProperties right in topcrm (Krzysztof) *) GMAC and SDIO on the matrixcrm controller need topcrm's ahb clock as parent. It is added to Matrix's binding and fixed in the driver *) LSP reset and pclk handling moved from clock child to mfd parent driver - Link to v8: https://lore.kernel.org/r/20260727-zx29clk-v8-0-7a107b00f1dd@gmail.com Changes in v8: *) Put #phy-cells into topcrm. The mfd child will have to assign itself the MFD parent's of_node to satisfy the check in phy-core.c's __of_phy_provider_register(). *) Added another register to matrixclk that controls in-controller distribution gates. No functional change, but it nicely confirms the top->matrix interface *) Changed clock indices to start at 0, adjusted driver to not use 0 as "do not export" marker. *) Rename DT fixed clock nodes from osc26m -> clock-26m and osc32k -> clock-32k *) Fixed more issues pointed out by Sashiko - Link to v7: https://lore.kernel.org/r/20260717-zx29clk-v7-0-408411cfcf36@gmail.com Changes in v7: *) Moved DT bindings back to clock/ (Krzysztof) *) Added a usb-phy child node to top to expose the USB status register *) Add clock gates that control input of PLL clocks into topcrm and forward to matrixcrm. Strip down matrixcrm inputs in the bindings to the known clocks in this register *) Add DDR clocks and resets, arm arch timer clock. They are marked critical and tell CCF not to gate off the aforementioned input/forward gates *) Remove syscon from matrixcrm (Krzysztof). The DDR mailbox system is on a different controller (soc_sys at 0x140000). ZTE's code merely controlled clocks in matrixcrm, which doesn't require syscon on this controller. *) Consistently use double quotes in bindings and full include paths (Krzysztof) The individual patches call out changes in more detail. - Link to v6: https://lore.kernel.org/r/20260702-zx29clk-v6-0-377b704f80c4@gmail.com Changes in v6: *) Use MFD for all 3 controllers - I hope both Conor and Philipp will agree. I kept top and matrix bindings in soc/zte and lsp in clock/ though. *) Clean up issues found by Sashiko. I pointed them out in the individual patches. They are localized fixes and don't affect the overall design *) Small code consistency: Changed "zx297520v3_lsp" to use "-" , "rst" in driver names to "reset" Changes in v5: *) Use MFD instead of aux bus for top and matrix clocks *) Move top and matrix bindings to soc/zte *) Give USB PHY its own resets *) Other localized changes are noted in the individual patches - Link to v4: https://lore.kernel.org/r/20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com Changes in v4: *) Use syscon and regmap instead of raw IO *) Move reset to its own driver on the aux bus, but keep reset and clk in the same binding as it matches the way the hardware works *) Go back to having matrixclk in its own device because syscon deals poorly with multi io reg devices. List all PLL outputs from topclk as inputs to matrixclk *) Some more hardware research: Figure out the parents of the 4 possible GPIO clock outputs and declare them in the driver. They are unused on the hardware I have, but they show that all PLLs can be used. - Link to v3: https://lore.kernel.org/r/20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com Changes in v3: Model top and matrix clocks as one device Add PLL driver Fixed a few issues found by Sashiko: register lock, some missing devm_, error handling v2: Fix build issues introduced by checkpatch.pl fixes that I didn't spot earlier. --- Stefan Dösinger (12): dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller ARM: dts: zte: Declare zx297520v3 CRM device nodes mfd: zx297520v3: Add a clock and reset MFD driver clk: zte: Add Clock registration infrastructure clk: zte: Add regmap-based clocks clk: zte: Add zx PLL support infrastructure clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 LSP clocks reset: zte: Add a zx297520v3 reset driver .../bindings/clock/zte,zx297520v3-lspcrm.yaml | 101 ++ .../bindings/clock/zte,zx297520v3-matrixcrm.yaml | 98 ++ .../bindings/clock/zte,zx297520v3-topcrm.yaml | 122 ++ MAINTAINERS | 9 + arch/arm/boot/dts/zte/zx297520v3.dtsi | 101 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 28 + drivers/clk/zte/Makefile | 6 + drivers/clk/zte/clk-regmap.c | 237 +++ drivers/clk/zte/clk-zx.c | 192 +++ drivers/clk/zte/clk-zx.h | 137 ++ drivers/clk/zte/clk-zx297520v3.c | 1599 ++++++++++++++++++++ drivers/clk/zte/pll-zx.c | 576 +++++++ drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile | 2 + drivers/mfd/zte-zx297520v3-crm.c | 101 ++ drivers/reset/Kconfig | 13 + drivers/reset/Makefile | 1 + drivers/reset/reset-zte-zx297520v3.c | 237 +++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 145 ++ include/dt-bindings/phy/zte,zx297520v3-topcrm.h | 12 + include/dt-bindings/reset/zte,zx297520v3-reset.h | 62 + 23 files changed, 3781 insertions(+), 12 deletions(-) --- base-commit: a8406e6c0b793ce0788019683837c40855b55995 change-id: 20260510-zx29clk-2e4d39e3128c Best regards, -- Stefan Dösinger