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Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v5 07/17] x86/extable: Add support for immediate form MSR instructions Date: Fri, 11 Sep 2026 10:42:01 +0200 Message-ID: <20260911084211.3149957-8-jgross@suse.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260911084211.3149957-1-jgross@suse.com> References: <20260911084211.3149957-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Rspamd-Queue-Id: B1ED71FE50 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -4.00 Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li V3: - use instruction decoder (Peter Zijlstra) V4: - don't assume %rax for immediate form (Andrew Cooper) V5: - drop stale comment (H. Peter Anvin) --- arch/x86/mm/extable.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index fa6eebe6a69e..9976ed01ce62 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -166,25 +166,54 @@ static bool ex_handler_uaccess(const struct exception_table_entry *fixup, static bool ex_handler_msr(const struct exception_table_entry *fixup, struct pt_regs *regs, bool wrmsr, bool safe, int reg) { + unsigned long *regptr; + struct insn insn; + bool imm_insn; + u32 msr; + + imm_insn = insn_decode_kernel(&insn, (void *)regs->ip) && + insn.vex_prefix.nbytes; + msr = imm_insn ? insn.immediate.value : (u32)regs->cx; + regptr = imm_insn ? insn_get_modrm_reg_ptr(&insn, regs) : ®s->ax; + if (unlikely(!regptr)) { + pr_err("Inconsistent %sMSR access instruction data at rIP: 0x%lx (%pS)!\n", + wrmsr ? "WR" : "RD", regs->ip, (void *)regs->ip); + show_stack_regs(regs); + goto out; + } + if (__ONCE_LITE_IF(!safe && wrmsr)) { - pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", - (unsigned int)regs->cx, (unsigned int)regs->dx, - (unsigned int)regs->ax, regs->ip, (void *)regs->ip); + u64 msr_val = *regptr; + + if (!imm_insn) { + /* + * On processors that support the Intel 64 architecture, the + * high-order 32 bits of each of RAX and RDX are ignored. + */ + msr_val &= 0xffffffff; + msr_val |= (u64)regs->dx << 32; + } + + pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%016llx) at rIP: 0x%lx (%pS)\n", + msr, msr_val, regs->ip, (void *)regs->ip); show_stack_regs(regs); } if (__ONCE_LITE_IF(!safe && !wrmsr)) { pr_warn("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", - (unsigned int)regs->cx, regs->ip, (void *)regs->ip); + msr, regs->ip, (void *)regs->ip); show_stack_regs(regs); } if (!wrmsr) { /* Pretend that the read succeeded and returned 0. */ - regs->ax = 0; - regs->dx = 0; + *regptr = 0; + + if (!imm_insn) + regs->dx = 0; } + out: if (safe) *pt_regs_nr(regs, reg) = -EIO; -- 2.55.0