From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E431B49B208; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470942; cv=none; b=lAEXIbzIo+O0E9JQDXSU9KUEMeT+0Yrbecg3usGBxuhXq8QsCFk9U/eqIhikc5AgwaTdCph+XokAUuuSg6atuWXRVMSOsWsN+zuQNeZBR9+1bqfUCbLZPaD/yz22U0dpQZRa8Z01CPqOgxwxI/yB3pWuYt/16CzZpS570hMnMac= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470942; c=relaxed/simple; bh=CHdPf6ttp8oRTNspmipbi6RxCjeRHb+9rUMleA8zgb4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fyL07dGnB2cx3egWkbgWO1Y7SuBNYKk1D4LkdEhQesvV22Vt89DhtnR0pQFUcAeodmcgiDmrY7xFvEhj1WtABguVGQKT6xPIVUSejY/j4zGeAiksVU0qJ2eg4d8CsphguzFRIRM9Mb9c/FUMFTe/1lBC9WKVGA4bXvfAvArgOYM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WQ0EBjMJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WQ0EBjMJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id B0BCCC2BCFF; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=CHdPf6ttp8oRTNspmipbi6RxCjeRHb+9rUMleA8zgb4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WQ0EBjMJ3VOwYF0YoULAfjLzG7YVAOQuMovf/uJvdtGE+bIfr0ArGRraSsIuotCzO 1RFZt5TQQZldA9jeoMmEwm5lOffQEbvFR/qk56vRjmc+ot/fsc339+T5lTvVVT6kbU e+u8xMcFoOluiVy309NflHnCKaYsdYmOK8E+J+SKiMtAoVX3QiSQCWAyaJbjfuuC69 TptU890IOP566UjnBINkdpsyx0EzqKD+NwgdACZX/sWMRT3NqhiEzVAsZNfzcNJEsY enfTwTlkc4V96GU4aDJaugxuVdkzcTUSHvawkIkzXBW3b+pPWVlTINM7Js02w1Uqrk +AQ2n/gXx4IAQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EE7BC88E53; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:43 +0800 Subject: [PATCH v7 13/15] serial: 8250_dw: add Ambarella CV75 quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-cv75-v5-v7-13-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=3195; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=TyYXNJamoUTysqAoDyQ16o7yw8rPZR1pbkI5mcWDXNQ=; b=cFaCJcredgGBXcBSwIuIfOzodofwhQx24frfan2HeXABZxotA7jj/M8fz+AFlpR+VMScLetO0 WwUU85oaxQoCuXsq5+up3Etlo3eangE1uCARNbFK9prNHCl3+e09e3w X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare licensed block. At the register level it is close enough to DW APB UART that a full custom UART driver is unnecessary: reuse 8250_dw with a small platform quirk. Quirks: - keep IER ETOI (bit 5) set for RX timeout behaviour - skip set_rate; baud clock is managed outside the UART block Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 5fba913f3301..19431c476c55 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -43,6 +43,9 @@ #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) +/* Ambarella IER: receive timeout interrupt enable */ +#define AMBARELLA_UART_IER_ETOI BIT(5) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) @@ -60,6 +63,7 @@ struct dw8250_platform_data { u8 usr_reg; + u8 ier_mask; u32 cpr_value; unsigned int quirks; }; @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_port *p) dw8250_writel_ext(up, RZN1_UART_RDMACR, val); } +static int dw8250_ier_mask_startup(struct uart_port *p) +{ + struct dw8250_data *d = to_dw8250_data(p->private_data); + struct uart_8250_port *up = up_to_u8250p(p); + int ret; + + ret = serial8250_do_startup(p); + if (ret) + return ret; + + /* + * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX + * timeout behaviour. + */ + up->ier |= d->pdata->ier_mask; + + return 0; +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { unsigned int quirks = data->pdata->quirks; @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) p->serial_in = dw8250_serial_in32; data->uart_16550_compatible = true; } + if (data->pdata->ier_mask) + p->startup = dw8250_ier_mask_startup; } static void dw8250_reset_control_assert(void *data) @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc10ee = { .quirks = DW_UART_QUIRK_IER_KICK, }; +static const struct dw8250_platform_data dw8250_ambarella_cv75_data = { + .usr_reg = DW_UART_USR, + .ier_mask = AMBARELLA_UART_IER_ETOI, + .quirks = DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { .usr_reg = DW_UART_USR, .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | @@ -889,6 +920,7 @@ static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { }; static const struct of_device_id dw8250_of_match[] = { + { .compatible = "ambarella,cv75-uart", .data = &dw8250_ambarella_cv75_data }, { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data }, -- 2.34.1