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From: Oleg Zadorozhnyi =0A= =0A= Report the phase difference between a PLL's reference and the PLL itself,= =0A= which is the loop's own residual error and therefore trends small on a=0A= locked device -- that is the measurement, not an artefact of it.=0A= =0A= The value comes from the on-chip time-to-digital converter, read through=0A= the debug window: unlock the window, point it at the converter, then read= =0A= the trigger register, which latches a fresh sample and returns the=0A= previous one. It is read three times per sample for that reason; a single= =0A= read hands back the sample from the last call, so a repeated measurement=0A= would look perfectly steady while saying nothing.=0A= =0A= Only the input a PLL has actually selected has a phase offset against it.= =0A= For any other pin there is nothing to measure and zero is reported,=0A= because the core abandons an entire pin dump on an error from any one pin.= =0A= =0A= Signed-off-by: Oleg Zadorozhnyi =0A= Assisted-by: Claude:claude-4-opus [chat]=0A= Signed-off-by: Ali Rouhi =0A= ---=0A= drivers/dpll/sit9531x/core.c | 148 +++++++++++++++++++++++++++++++++++=0A= drivers/dpll/sit9531x/dpll.c | 102 ++++++++++++++++++++++++=0A= drivers/dpll/sit9531x/regs.h | 38 +++++++++=0A= 3 files changed, 288 insertions(+)=0A= =0A= diff --git a/drivers/dpll/sit9531x/core.c b/drivers/dpll/sit9531x/core.c=0A= index 46179a9e13c3..356d1eac4ec5 100644=0A= --- a/drivers/dpll/sit9531x/core.c=0A= +++ b/drivers/dpll/sit9531x/core.c=0A= @@ -2132,6 +2132,154 @@ int sit9531x_output_pulse_ctrl_set(struct sit9531x_= dev *sitdev,=0A= return rc;=0A= }=0A= =0A= +/*=0A= + * sit9531x_phase_offset_read - read phase difference via TDC=0A= + * @phase_ps: output phase difference in picoseconds=0A= + *=0A= + * Reads the Time-to-Digital Converter (TDC) signed 35-bit code from the= =0A= + * PLL page registers, then converts to picoseconds using the VCO=0A= + * frequency: phase_diff =3D tdc_code / fvco.=0A= + *=0A= + * Caller must hold sitdev->multiop_lock.=0A= + */=0A= +int sit9531x_phase_offset_read(struct sit9531x_dev *sitdev, u8 pll_idx,=0A= + s64 *phase_ps)=0A= +{=0A= + u64 fvco, mag_ps;=0A= + s64 tdc_signed;=0A= + u64 tdc_raw;=0A= + int rc, lock_rc, i;=0A= + bool sign;=0A= + u8 v;=0A= +=0A= + lockdep_assert_held(&sitdev->multiop_lock);=0A= +=0A= + if (pll_idx >=3D SIT9531X_NUM_PLLS)=0A= + return -EINVAL;=0A= +=0A= + /* Unlock the debug page so the TDC registers are accessible. */=0A= + rc =3D sit9531x_write_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DEBUG,=0A= + SIT9531X_PLL_DEBUG_UNLOCK);=0A= + if (rc)=0A= + goto relock;=0A= +=0A= + /*=0A= + * Select the debug clock for taps below 200 kHz, then point the=0A= + * readback at the TDC. Only the one bit is touched: writing the=0A= + * modifier register whole would clear the fields belonging to=0A= + * other taps.=0A= + */=0A= + rc =3D sit9531x_update_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_WRITE_CODE,=0A= + SIT9531X_DBG_LOW_FREQ_CLK_BIT,=0A= + SIT9531X_DBG_LOW_FREQ_CLK_BIT);=0A= + if (rc)=0A= + goto relock;=0A= + rc =3D sit9531x_write_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_READ_CODE,=0A= + SIT9531X_DBG_READ_CODE_TDC);=0A= + if (rc)=0A= + goto relock;=0A= +=0A= + /*=0A= + * Latch a sample by reading the trigger register. A single=0A= + * read returns the previous latch, so read it three times as=0A= + * the documented phase-difference procedure does.=0A= + */=0A= + for (i =3D 0; i < SIT9531X_DBG_LATCH_READS; i++) {=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_TRIGGER, &v);=0A= + if (rc)=0A= + goto relock;=0A= + }=0A= +=0A= + tdc_raw =3D 0;=0A= +=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_DATA_4, &v);=0A= + if (rc)=0A= + goto relock;=0A= + sign =3D !!(v & BIT(SIT9531X_TDC_SIGN_BIT));=0A= + tdc_raw =3D (u64)(v & SIT9531X_TDC_MAG_HI_MASK) << 32;=0A= +=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_DATA_3, &v);=0A= + if (rc)=0A= + goto relock;=0A= + tdc_raw |=3D (u64)v << 24;=0A= +=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_DATA_2, &v);=0A= + if (rc)=0A= + goto relock;=0A= + tdc_raw |=3D (u64)v << 16;=0A= +=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_DATA_1, &v);=0A= + if (rc)=0A= + goto relock;=0A= + tdc_raw |=3D (u64)v << 8;=0A= +=0A= + rc =3D sit9531x_read_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DBG_DATA_0, &v);=0A= + if (rc)=0A= + goto relock;=0A= + tdc_raw |=3D v;=0A= +=0A= + /*=0A= + * Apply sign. Per the register map the sign bit is active-high=0A= + * for a positive offset: bit set -> +code, bit clear -> -code.=0A= + */=0A= + tdc_signed =3D sign ? (s64)tdc_raw : -(s64)tdc_raw;=0A= +=0A= + /*=0A= + * Get VCO frequency for conversion. -ENODATA means DIVN is not=0A= + * programmed (PLL unused on this board) -- skip silently rather=0A= + * than spamming the log on every poll cycle. A register access=0A= + * failure is returned as an error, not folded into a fabricated=0A= + * 0 ps measurement.=0A= + */=0A= + rc =3D sit9531x_get_fvco(sitdev, pll_idx, &fvco);=0A= + if (rc =3D=3D -ENODATA) {=0A= + dev_dbg(sitdev->dev, "PLL%c: Fvco unknown, skip TDC\n",=0A= + 'A' + pll_idx);=0A= + rc =3D -ENODEV;=0A= + goto relock;=0A= + }=0A= + if (rc)=0A= + goto relock;=0A= +=0A= + /*=0A= + * phase_diff (seconds) =3D tdc_code / fvco=0A= + * phase_diff (ps) =3D tdc_code * 1e12 / fvco=0A= + *=0A= + * mul_u64_u64_div_u64() keeps the exact Hz denominator; dividing=0A= + * by whole MHz instead would lose up to ~40 ppm of scale on a=0A= + * fractional-DIVN Fvco.=0A= + */=0A= + mag_ps =3D mul_u64_u64_div_u64(tdc_signed < 0 ? -tdc_signed : tdc_signed,= =0A= + 1000000000000ULL, fvco);=0A= + *phase_ps =3D tdc_signed < 0 ? -(s64)mag_ps : (s64)mag_ps;=0A= +=0A= + rc =3D 0;=0A= +=0A= +relock:=0A= + /*=0A= + * Close the debug window again. The key register opens every debug=0A= + * register on this PLL while it holds the unlock value, and this read=0A= + * runs on every pin-get of a connected input, so leaving it open=0A= + * would mean normal monitoring permanently unlocks the block.=0A= + */=0A= + lock_rc =3D sit9531x_write_pll_u8(sitdev, pll_idx,=0A= + SIT9531X_PLL_REG_DEBUG,=0A= + SIT9531X_PLL_DEBUG_LOCK);=0A= + if (lock_rc && !rc)=0A= + rc =3D lock_rc;=0A= +=0A= + return rc;=0A= +}=0A= +=0A= /*=0A= * sit9531x_ref_state_fetch - read input reference status from hardware=0A= * @index: logical input index=0A= diff --git a/drivers/dpll/sit9531x/dpll.c b/drivers/dpll/sit9531x/dpll.c=0A= index 0cad081eb599..1dfd83b635e2 100644=0A= --- a/drivers/dpll/sit9531x/dpll.c=0A= +++ b/drivers/dpll/sit9531x/dpll.c=0A= @@ -603,6 +603,107 @@ sit9531x_dpll_input_pin_prio_set(const struct dpll_pi= n *pin, void *pin_priv,=0A= return 0;=0A= }=0A= =0A= +/*=0A= + * sit9531x_dpll_input_pin_phase_offset_get - phase offset of a reference= =0A= + *=0A= + * What this reports, and what it deliberately does not:=0A= + *=0A= + * The ABI defines the attribute as the phase difference between the signa= l=0A= + * on a pin and its parent DPLL device, so this is the loop's own residual= =0A= + * error, sampled with the loop closed. On a locked DPLL it therefore=0A= + * trends small -- that is the measurement, not an artefact of it. The=0A= + * framework expects successive values to be averaged, which suits a=0A= + * closed-loop residual and not a one-shot open-loop capture.=0A= + *=0A= + * The chip can also measure the reference against the local oscillator=0A= + * with the outer loop's correction frozen, which is a different quantity= =0A= + * and the one the documented phase-difference procedure produces. That= =0A= + * needs the digital loop filter held (and, on the 1PPS PLL, the automatic= =0A= + * phase- and frequency-lock helpers held off), which leaves the PLL=0A= + * undisciplined until it is released. A netlink read must not do that,= =0A= + * so the open-loop measurement lives in a debugfs helper that owns the=0A= + * freeze and restores it; it is not this callback.=0A= + *=0A= + * Precondition, which this callback cannot create: the TDC compares=0A= + * against a signal the PLL drives, so a PLL driving no output with its=0A= + * zero-delay buffer off has nothing to measure. SiTime confirms this is= =0A= + * a property of the hardware rather than of their measurement script.=0A= + * The script satisfies it by mapping a spare output and restarting the=0A= + * PLL -- side effects that do not belong in a getter, so a reading taken= =0A= + * in that state is simply not meaningful.=0A= + *=0A= + * Non-selected pins and a PLL with no programmed divider report zero=0A= + * rather than an error: the DPLL core propagates any error from this=0A= + * callback and fails the whole pin dump with it, unlike the frequency=0A= + * offset getter, where -ENODATA makes the core omit the attribute. There= =0A= + * is no per-pin "no data" for phase offset, so it is a value or no=0A= + * callback at all.=0A= + */=0A= +static int=0A= +sit9531x_dpll_input_pin_phase_offset_get(const struct dpll_pin *pin,=0A= + void *pin_priv,=0A= + const struct dpll_device *dpll,=0A= + void *dpll_priv, s64 *phase_offset,=0A= + struct netlink_ext_ack *extack)=0A= +{=0A= + struct sit9531x_dpll_pin *dpin =3D pin_priv;=0A= + struct sit9531x_dpll *sitdpll =3D dpll_priv;=0A= + struct sit9531x_dev *sitdev =3D sitdpll->dev;=0A= + enum dpll_pin_state state;=0A= + s64 offset;=0A= + int rc;=0A= +=0A= + mutex_lock(&sitdev->multiop_lock);=0A= +=0A= + /*=0A= + * The on-chip TDC is a per-PLL resource that always measures the=0A= + * phase difference between the VCO and the PLL's currently=0A= + * selected reference; it cannot be pointed at an arbitrary input.=0A= + * For any input that is not the active reference there is no=0A= + * meaningful per-pin phase offset, so report 0 instead of the=0A= + * active reference's value.=0A= + */=0A= + sit9531x_dpll_selection_state_get(sitdev, sitdpll, dpin->id, &state);=0A= + if (state !=3D DPLL_PIN_STATE_CONNECTED) {=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= + dpin->phase_offset =3D 0;=0A= + *phase_offset =3D 0;=0A= + return 0;=0A= + }=0A= +=0A= + rc =3D sit9531x_phase_offset_read(sitdev, sitdpll->id, &offset);=0A= + mutex_unlock(&sitdev->multiop_lock);=0A= +=0A= + /*=0A= + * -ENODEV means the PLL has no programmed DIVN (unused on this=0A= + * board); report phase_offset =3D 0 so a full pin-get dump does not=0A= + * fail just because one DPLL is dormant.=0A= + */=0A= + if (rc =3D=3D -ENODEV) {=0A= + dpin->phase_offset =3D 0;=0A= + *phase_offset =3D 0;=0A= + return 0;=0A= + }=0A= + if (rc) {=0A= + NL_SET_ERR_MSG(extack, "TDC phase readback failed");=0A= + return rc;=0A= + }=0A= +=0A= + /*=0A= + * The ABI reports phase offset in units of 1/DPLL_PHASE_OFFSET_DIVIDER= =0A= + * picoseconds: the integer part of the attribute is the value divided=0A= + * by the divider, the remainder is the fraction. The TDC resolves one= =0A= + * VCO period (hundreds of picoseconds), so the fractional digits are=0A= + * always zero here, but the magnitude still has to be scaled or every=0A= + * reading would be reported a thousand times too small.=0A= + */=0A= + offset *=3D DPLL_PHASE_OFFSET_DIVIDER;=0A= +=0A= + dpin->phase_offset =3D offset;=0A= + *phase_offset =3D offset;=0A= + return 0;=0A= +}=0A= +=0A= static const struct dpll_pin_ops sit9531x_dpll_input_pin_ops =3D {=0A= .direction_get =3D sit9531x_dpll_input_pin_direction_get,=0A= .frequency_get =3D sit9531x_dpll_input_pin_frequency_get,=0A= @@ -610,6 +711,7 @@ static const struct dpll_pin_ops sit9531x_dpll_input_pi= n_ops =3D {=0A= .state_on_dpll_set =3D sit9531x_dpll_input_pin_state_on_dpll_set,=0A= .prio_get =3D sit9531x_dpll_input_pin_prio_get,=0A= .prio_set =3D sit9531x_dpll_input_pin_prio_set,=0A= + .phase_offset_get =3D sit9531x_dpll_input_pin_phase_offset_get,=0A= };=0A= =0A= /*=0A= diff --git a/drivers/dpll/sit9531x/regs.h b/drivers/dpll/sit9531x/regs.h=0A= index 9d515e109feb..08eae8a2c279 100644=0A= --- a/drivers/dpll/sit9531x/regs.h=0A= +++ b/drivers/dpll/sit9531x/regs.h=0A= @@ -271,6 +271,44 @@=0A= #define SIT9531X_PLL_REG_DIVN_NUM 0x32 /* 4 bytes (0x32-0x35) */=0A= #define SIT9531X_PLL_REG_DIVN_DEN 0x38 /* 4 bytes (0x38-0x3B) */=0A= =0A= +/* Debug register unlock */=0A= +#define SIT9531X_PLL_REG_DEBUG 0xBD=0A= +#define SIT9531X_PLL_DEBUG_UNLOCK 0xC3=0A= +#define SIT9531X_PLL_DEBUG_LOCK 0x00=0A= +=0A= +/*=0A= + * Signal pathway debug readback -- PLL page. Dig_Sys_ReadCode selects=0A= + * which point of the pathway is tapped, Dig_Sys_WriteCode carries the=0A= + * modifiers for that read, Dig_Sys_read7..read0 hold the sampled bytes=0A= + * and the trigger register latches a sample. The TDC phase=0A= + * measurement is one tap among several, reached through read code 69.=0A= + */=0A= +#define SIT9531X_PLL_REG_DBG_READ_CODE 0xB3=0A= +#define SIT9531X_PLL_REG_DBG_WRITE_CODE 0xB4=0A= +#define SIT9531X_DBG_LOW_FREQ_CLK_BIT BIT(7)=0A= +#define SIT9531X_PLL_REG_DBG_DATA_0 0xB5 /* [7:0] */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_1 0xB6 /* [15:8] */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_2 0xB7 /* [23:16] */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_3 0xB8 /* [31:24] */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_4 0xB9 /* [34:32] + sign */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_5 0xBA /* [47:40] */=0A= +#define SIT9531X_PLL_REG_DBG_DATA_6 0xBB=0A= +#define SIT9531X_PLL_REG_DBG_DATA_7 0xBC=0A= +#define SIT9531X_PLL_REG_DBG_TRIGGER 0xD0 /* read to latch a sample */= =0A= +=0A= +/*=0A= + * Reads of the trigger needed to latch a fresh sample. One returns the= =0A= + * previous latch, which the documented procedures work around by reading = it=0A= + * three times.=0A= + */=0A= +#define SIT9531X_DBG_LATCH_READS 3=0A= +#define SIT9531X_DBG_DATA_BYTES 8=0A= +=0A= +/* Read code of the TDC phase tap, and the sign bit of its sample */=0A= +#define SIT9531X_DBG_READ_CODE_TDC 69=0A= +#define SIT9531X_TDC_SIGN_BIT 3=0A= +#define SIT9531X_TDC_MAG_HI_MASK GENMASK(2, 0)=0A= +=0A= /*=0A= * DIVN carried as fixed point, and the unit the DPLL ABI wants the=0A= * fractional frequency offset in. Equal in value, distinct in meaning.= =0A= -- =0A= 2.39.2 (Apple Git-143)=0A= =0A=