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Tue, 15 Sep 2026 00:13:12 -0700 (PDT) Received: from center.jhjvjihww5qejoy14qwv1cc4td.frax.internal.cloudapp.net ([131.189.143.225]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d284a7bsm117889265e9.3.2026.09.15.00.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 00:13:12 -0700 (PDT) From: Orgad Shaneh To: tsbogend@alpha.franken.de Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX Date: Tue, 15 Sep 2026 07:12:44 +0000 Message-ID: <20260915071306.15006-1-orgads@gmail.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The L2 helpers pick between the OCTEON II and the CN3XXX/CN5XXX register model with OCTEON_IS_MODEL(OCTEON_CN63XX), which matches the CN63XX only. Every other OCTEON II part - CN66XX, CN68XX, CN61XX - takes the CN3XXX/CN5XXX branch and touches registers that do not exist on it: L2C_DBG, L2C_LCKBASE, L2C_LCKOFF and L2C_SPAR4 instead of the LCKL2 cache operation, the L2C_WPAR_{PPX,IOBX} way-partitioning registers and L2C_TADX_TAG. On a CN6635 board cvmx_l2c_lock_line(), called from prom_init() under CONFIG_CAVIUM_OCTEON_LOCK_L2 to lock the TLB refill and exception vectors, therefore went through L2C_DBG/L2C_LCKBASE. Whatever those writes hit inside the L2 controller left it silently dropping stores to DRAM above 512 MB: a probe that wrote 0x20400000, 0x40000000, 0x80000000 and 0xe0000000 in prom_init read its values back before the lock block and the old contents right after it, on CCA 0, 2 and 3 alike, while writes below 256 MB and every u-boot "mw" stuck. Since the cvmx bootmem free list keeps its nodes inside the free blocks themselves, the kernel's first split above 0x20000000 was lost, the walk of the free list stopped there, and the board came up with 248 MB of its 8 GB. Match the whole CN6XXX family, which is what these register accesses are keyed to. The CN63XX keeps exactly the same path. The geometry helpers in this file need the same treatment but not the same condition; they are handled in the next patch. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh --- diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c --- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c +++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c @@ -54,7 +54,7 @@ int cvmx_l2c_get_core_way_partition(uint32_t core) if (core >= cvmx_octeon_num_cores()) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff; /* @@ -91,14 +91,14 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) mask &= valid_mask; /* A UMSK setting which blocks all L2C Ways is an error on some chips */ - if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN6XXX)) return -1; /* Validate the core number */ if (core >= cvmx_octeon_num_cores()) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); return 0; } @@ -147,10 +147,10 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask) mask &= valid_mask; /* A UMSK setting which blocks all L2C Ways is an error on some chips */ - if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN6XXX)) return -1; - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); else cvmx_write_csr(CVMX_L2C_SPAR4, @@ -160,7 +160,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask) int cvmx_l2c_get_hw_way_partition(void) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff; else return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF); @@ -313,7 +313,7 @@ static void fault_in(uint64_t addr, int len) int cvmx_l2c_lock_line(uint64_t addr) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT; uint64_t assoc = cvmx_l2c_get_num_assoc(); uint64_t tag = addr >> shift; @@ -460,7 +460,7 @@ void cvmx_l2c_flush(void) int cvmx_l2c_unlock_line(uint64_t address) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { int assoc; union cvmx_l2c_tag tag; uint32_t tag_addr; @@ -661,7 +661,7 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index) (int)index, cvmx_l2c_get_num_sets()); return tag; } - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { union cvmx_l2c_tadx_tag l2c_tadx_tag; uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) | @@ -745,7 +745,7 @@ uint32_t cvmx_l2c_address_to_index(uint64_t addr) } if (indxalias) { - if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1< select the way of the cache block involved in -- 2.47.0