From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CB124F30CF; Fri, 18 Sep 2026 11:35:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731306; cv=none; b=KUa3ct3inyVG47yX3w3yK+t1fvmNw7k+U/F+i9/PcGf4RQin2TMjEyInvdx58RCjgA10BP79rRbMq92o7ZOmlxDZlzRf2y+1eMk/Ue/NpuJsNGu31MQHIJ1uoOsumTfYe1Mb/1TsRS2maF99JTEpVu6Bwy3H3/N+mWGVHRVTcXQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789731306; c=relaxed/simple; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cR1sRGwPLKMlWUSdAbF9Aegi/0xqMA+Wk7qIvAdLtch2MgjwnWigVG2Yc1iWOFCnVhVdmKMwZaRe6QFYDyEqiAMeVekrm/ErgEinQ0JwpbMM2h8x8HV79g12Utt/nPIm2BzCx9AJDD1m09pNhIWWTOuAioL47BhxcjTpARFAC+c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Zgkx/100; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Zgkx/100" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731305; x=1821267305; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pLLUnpsQHk0XLLoB+wBplrU8A7WIjOzUca/wCfOw6mw=; b=Zgkx/100fRkZE5bLWIi8J526ylPkF/prTEVeeSEa5JUV2qyqXZXYNiR9 7tKBZTHEXGqgzPDyBZsjRueu7em+RKYhf8IofzrgMg30UQTsiDu664pZB tZLuJOQr32BA3896Ljb21QdFZRb3jCgEnnUTYlaokXOAoMIrnZhZCBsR3 A9SQ2q8acFCOVkKGbGRvvFj3trUBlq8l2q7JIrAAfuznunWOxlpxPVVX/ Z3BOubhKtUdTjx34Ep3F9rWGysKGNcTTe3M4xDRL5HSPukuwaiElQ3icP tm+VVdp0TPVRrQkWwq38+nwu3bIGnaNnRd5cjjRuMAVN1TR7ldD2Z9Dse A==; X-CSE-ConnectionGUID: UKadeTgMQlCsweVzlz2kNA== X-CSE-MsgGUID: nwVHFmhVRnuLz53ZcMhigg== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="295223747" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:35:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Fri, 18 Sep 2026 04:35:03 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:59 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:34:05 +0200 Subject: [PATCH net-next v7 13/14] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260918-lan966x-pci-fdma-v7-13-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 7b196b0a0eb6..7bb726550caf 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, + reg = <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; -- 2.34.1