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[46.193.35.178]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4886876c500sm374681f8f.19.2026.09.22.11.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 11:44:58 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: Abel Vesa , Brian Masney , Jerome Brunet , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/4] dt-bindings: clock: Add LPASSCC and reset controller for Glymur Date: Tue, 22 Sep 2026 19:44:23 +0100 Message-ID: <20260922184425.56114-3-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260922184425.56114-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 2_4IJ2gu2BX1cBB6aJCoKoHG3MP0V6pW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX4yvP+cXHpqQz /AEq3++Uu2k2bi6txpRkvxdRsj4mC3pXNdKt1K2GOg46K3d+ffbB/4Lw5a2/InoR4wKwYYlBEda LUHSq9DYzO+MEUSdC+6IhAfekkZRw+dwVkXn4Q/zk2yoqLcZeHbb5jaCj68eJPEtY54dr6bwRpA JiSAi1nQQyT7b6MUCfmgZDFtH+hyid/vyZDRftNARMJCv8N38TDAGrbelSeQNGmpn+4n3Nwzpas 1xxTXrNWx+Tjp+R3Oy6h5HoQHqHNEjzNI5TaztQkvrx0Q3BTs+BW3ooTyZQpbeoD2GwcD1WEBud 5nCHDtLxDVAQA3Z9hz0jk+U206Ba1SPGxwIhxajuh55nKGo2vPV0CCLoLlhimy9UCt5vRjeFh1u RC+wCUe+mtcQ/ingK1OEdJxdCARYye6jKbFuSyGXdbPVm+WgjfIeQroN2n7kVJt/XjsMJU9kc2G 9HFZNBB0bc2QlVGUjKQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDI3NSBTYWx0ZWRfX9P8KX/Qd2DOu FvE40YI2qPe3FopoFIYBZOVe7O1J8a7DSy56Pgb+hIGP6PbGU9Z2DMPSNdCtgRgBmAfA0Reuiqu k/bNAip+SSZpghENwzOOJyzQmo798IU= X-Authority-Analysis: v=2.4 cv=SuAFe/O0 c=1 sm=1 tr=0 ts=6ab2ccad cx=c_pps a=+D9SDfe9YZWTjADjLiQY5g==:117 a=Hji71o54RgNgZYqDgtlrhw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=-l7Lzzg0JijIaF3KBckA:9 a=vmgOmaN-Xu0dpDh8OwbV:22 X-Proofpoint-ORIG-GUID: 2_4IJ2gu2BX1cBB6aJCoKoHG3MP0V6pW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-22_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220275 The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/clock/qcom,glymur-lpasscc.yaml | 10 ++++++++++ include/dt-bindings/clock/qcom,glymur-lpasscc.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml index c047c0174a93..916ab1b3dbee 100644 --- a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - qcom,glymur-lpassaudiocc + - qcom,glymur-lpasscc reg: maxItems: 1 @@ -47,4 +48,13 @@ examples: #clock-cells = <1>; #reset-cells = <1>; }; + + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,glymur-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; ... diff --git a/include/dt-bindings/clock/qcom,glymur-lpasscc.h b/include/dt-bindings/clock/qcom,glymur-lpasscc.h index 3006b12e385e..3fc8e7313cab 100644 --- a/include/dt-bindings/clock/qcom,glymur-lpasscc.h +++ b/include/dt-bindings/clock/qcom,glymur-lpasscc.h @@ -13,4 +13,7 @@ #define LPASS_AUDIO_SWR_WSA3_CGCR 3 #define LPASS_AUDIO_SWR_WSA4_CGCR 4 +/* LPASS CC CSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + #endif -- 2.53.0