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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3FQw6G3NbIw+G5Pk4/l86mT6DsIAsGRuFP5/V+gXNDeBoBBMC2f3otMjZWaee3zjt4Goc8f0fr5hXTQy2KR406IRIyFu1+Gl/vuS4v4iQ7If6Mx6ISuL8pBPOD3vwfuq1m/GRzdOqsCw9i2zeEjVH8dxrcCR61i5yqvXvMcBFw8F+gz8Yl1unJsajQN+EmnXb+4vK0jKf/QSFkIwgmE1tLuG2vs7owEC+6lDYwwQ5QtLXQkcHTwjGnAX2I82pw4KPa7eziCLQ5+2tDa2J6SYkf5Hu7Dr38xcoOriKuPHbnVg1FmrRWV+fESpmNcZfqXnY86O5hAJr38yiFGSksmIqDCzHLPaAkmtN/xrEfkhIPqZJMbrZV+IQJfhdP/0ZsDeZOKJR+O3s1Q2iX0B4fgeZZ5HQDWRrWY9Olsrmvt67fXn4ZnIykj02KdNrs/LdbSq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:19:29.7669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9b5e3f9-4e36-421f-c771-08df1943021e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8158 Tegra no longer uses the DesignWare field shift macros after converting the call sites to FIELD_PREP() and FIELD_MODIFY(). Remove the unused shift macros and the old narrow event-selector mask. Add the complete event-selector field with the standard mask name, and keep a temporary alias so existing users keep building until they are converted. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-designware.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index c4db241547be..f70b7da97e07 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -82,9 +82,7 @@ #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) #define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n) #define PORT_AFR_ENTER_ASPM BIT(30) -#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 #define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) -#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) #define PCIE_PORT_LINK_CONTROL 0x710 @@ -151,7 +149,6 @@ #define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) -#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) #define GEN3_EQ_CONTROL_OFF 0x8A8 @@ -277,17 +274,14 @@ #define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8 #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 -#define EVENT_COUNTER_ENABLE_SHIFT 2 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) -#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) -#define EVENT_COUNTER_EVENT_SEL_SHIFT 16 -#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 #define EVENT_COUNTER_EVENT_L1_1 0x7 #define EVENT_COUNTER_EVENT_L1_2 0x8 -#define EVENT_COUNTER_GROUP_SEL_SHIFT 24 #define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_GROUP_5 0x5 -- 2.34.1