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This is needed since this controller differs from the existing designware i2c (DW_apb_i2c [1]) in its register offsets and some register definitions. The new compatible updates driver logic due to changes in register definitions: - The new register offsets are handled by first refactoring the driver to use a map of register IDs to their offsets. - Similarly, also update the driver to use an updated CON-register bitfield definition. - Interrupts are acknowledged by writing a bitmask to a single CLR_INTR register instead of reading N dedicated CLR_* registers; i2c_dw_ack_intr() picks the right method based on dev->flags. - One HCNT/LCNT register pair is shared between standard and fast speed instead of having one pair each; i2c_dw_write_timings() writes whichever value set matches the configured speed. - No COMP_PARAM_1 register, so FIFO depth and high-speed-mode support can't be autodetected: FIFO depth now comes from the required snps,tx-fifo-depth/snps,rx-fifo-depth DT properties, and the high-speed capability check is skipped. - No defined CON.RESTART_EN bit; treat it as always set. - TDA54 SoC does not support SMBus, so skip accesses to those registers. [0]: DWC_i2c_reference.pdf [1]: DW_apb_i2c_databook.pdf Signed-off-by: Aniket Limaye --- Changes in v3: - [PATCH 2/3] Revert to special handling for the max_register in regmap for MODEL_AMD_NAVI_GPU instead of unconditionally including AMD_UCSI_INTR_REG in the legal regmap range. (sashiko) - Link to v2: https://lore.kernel.org/r/20260925-tda54-upstream-i2c-v2-0-261785e58493@ti.com Changes in v2: - Rename compatible/flag: snps,dwc-i2c -> ti,tda54-i2c, MODEL_DWC_I2C -> MODEL_TI_TDA54. - Move the Reg ID -> Offset mapping inside the regmap functions such that existing calls to reg_read/write are unaltered. This does change the reg_read()/reg_write() functions to take reg IDs as input rather than their physical offsets, which also requires updates to the xe_i2c.c driver to handle the same mapping. - Remove i2c_dwc_has_smbus(); just skip the SMBUS_INTR_MASK write under MODEL_TI_TDA54. - Link to v1: https://lore.kernel.org/r/20260919-tda54-upstream-i2c-v1-0-b0b9f77be18b@ti.com --- Aniket Limaye (3): dt-bindings: i2c: dw: Add ti,tda54-i2c compatible i2c: designware: Support per-variant reg/bit offsets and intr handling i2c: designware: Add ti,tda54-i2c support .../bindings/i2c/snps,designware-i2c.yaml | 33 ++++ drivers/gpu/drm/xe/regs/xe_i2c_regs.h | 3 +- drivers/i2c/busses/i2c-designware-amdisp.c | 1 + drivers/i2c/busses/i2c-designware-common.c | 193 ++++++++++++++++++--- drivers/i2c/busses/i2c-designware-core.h | 70 +++++++- drivers/i2c/busses/i2c-designware-master.c | 78 +++++---- drivers/i2c/busses/i2c-designware-pcidrv.c | 2 + drivers/i2c/busses/i2c-designware-platdrv.c | 3 + drivers/i2c/busses/i2c-designware-slave.c | 26 +-- include/linux/designware_i2c.h | 137 ++++++++++----- 10 files changed, 432 insertions(+), 114 deletions(-) --- base-commit: 587858367581b9c55c3690f4e63382ad622719d4 change-id: 20260919-tda54-upstream-i2c-d0c67f16b4fc Best regards, -- Aniket Limaye