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Fri, 25 Sep 2026 01:46:47 -0700 (PDT) Received: from debian ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a64f9bcsm5281953f8f.32.2026.09.25.01.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 01:46:47 -0700 (PDT) From: Srinivas Kandagatla To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Abel Vesa , Abel Vesa , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 1/4] dt-bindings: clock: Add LPASS AUDIOCC and reset controller for Glymur Date: Fri, 25 Sep 2026 09:46:32 +0100 Message-ID: <20260925084635.112399-2-srinivas.kandagatla@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260925084635.112399-1-srinivas.kandagatla@oss.qualcomm.com> References: <20260925084635.112399-1-srinivas.kandagatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDAzNCBTYWx0ZWRfX2fcNcoJ4OOpy OyNMBNQEHdmKd/5PWMBgTpEsp3nvi+uxyoLgUiTxtr/S9gl5NJ10FRW6IgmPYSO9y0APljCpGav AKSxr3rfH1+D9s+rew8DLSDJjmCJX9UelYJdVB+tsICLF1N0OYLsLkd/E5IvLIkYMSSAPFSXF3v vPjQHT+soYUNGwWdFFOj5Sv38JwY0i5onwevmqCoj9JoGDhUNKG+4OotgUMyDhhB+e02LtmsmqB 9pIY7Q46RFkuRPwF1kY/FFoFDUkiEaXOTDTpSc8VccK4MkP1wwD1UwdT1zhWLoGzPbdRqK1zMPk rggFWGJbDhJRxanU5+CXQ+tJcguzNcdQqSLo2ui2ZN31GXJSFJFBHjKhZXzd99s6WEGuFoy1taG VdjIFKMcQb++HyAP7ZiGwj3ZLYmTMY7kMJyhKicnBNZko4nAas5A6MhdsQRbSuGzDPWfzBrR9jL P4ckAyjaspDabyE8nGQ== X-Proofpoint-GUID: Nid7uQQAsbkbgmNYMLxfy3ZzupQkQ5U_ X-Proofpoint-ORIG-GUID: Nid7uQQAsbkbgmNYMLxfy3ZzupQkQ5U_ X-Authority-Analysis: v=2.4 cv=XawcX455 c=1 sm=1 tr=0 ts=6ab634f9 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=ZsC4DHZuhs/kKio7QBcDoQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=yiKMOllxs-7wBVDooBUA:9 a=IoWCM6iH3mJn3m4BftBB:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDAzNCBTYWx0ZWRfX8IXbJjZ6AxTp CTKTcGT4yxkoAZQN9BLWmtlFpng32X0wsOOsCdGlfYnYeEcL6TlSnB/R5U2S9xOm4ghDWZz7n5Q X9cZ4WFqQsIaLPqPthZUB+5A1lmOHnw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250034 The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../bindings/clock/qcom,glymur-lpasscc.yaml | 50 +++++++++++++++++++ .../dt-bindings/clock/qcom,glymur-lpasscc.h | 16 ++++++ 2 files changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-lpasscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml new file mode 100644 index 000000000000..c047c0174a93 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on Glymur + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on Glymur. + + See also: + include/dt-bindings/clock/qcom,glymur-lpasscc.h + +properties: + compatible: + enum: + - qcom,glymur-lpassaudiocc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,glymur-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-lpasscc.h b/include/dt-bindings/clock/qcom,glymur-lpasscc.h new file mode 100644 index 000000000000..3006b12e385e --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-lpasscc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_GLYMUR_H + +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA1_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 +#define LPASS_AUDIO_SWR_WSA3_CGCR 3 +#define LPASS_AUDIO_SWR_WSA4_CGCR 4 + +#endif -- 2.53.0