// SPDX-License-Identifier: (GPL-2.0-only OR MIT)

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/allwinner,sun60i-a733-ccu.h>
#include <dt-bindings/clock/allwinner,sun60i-a733-r-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/allwinner,sun60i-a733-ccu.h>
#include <dt-bindings/reset/allwinner,sun60i-a733-r-ccu.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x000>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu1: cpu@100 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu2: cpu@200 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu3: cpu@300 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu4: cpu@400 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu5: cpu@500 {
			compatible = "arm,cortex-a55";
			device_type = "cpu";
			reg = <0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <530>;
		};

		cpu6: cpu@600 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			reg = <0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
		};

		cpu7: cpu@700 {
			compatible = "arm,cortex-a76";
			device_type = "cpu";
			reg = <0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
		};
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		arm,no-tick-in-suspend;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x40000000>;

		pio: pinctrl@2000000 {
			compatible = "allwinner,sun60i-a733-pinctrl";
			reg = <0x02000000 0x600>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_APB1>, <&hosc>, <&rtc CLK_OSC32K>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				allwinner,pinmux = <2>;
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			uart0_pb9_pb10_pins: uart0-pb9-pb10-pins {
				pins = "PB9", "PB10";
				allwinner,pinmux = <2>;
				function = "uart0";
			};
		};

		ccu: clock-controller@2002000 {
			compatible = "allwinner,sun60i-a733-ccu";
			reg = <0x02002000 0x2000>;
			clocks = <&hosc>, <&rtc CLK_OSC32K>,
				 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>;
			clock-names = "hosc", "losc", "iosc", "losc-fanout";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		uart0: serial@2500000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x02500000 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		gic: interrupt-controller@3400000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x03400000 0x10000>,
			      <0x03460000 0x100000>;
		};

		mmc0: mmc@4020000 {
			compatible = "allwinner,sun60i-a733-mmc",
				     "allwinner,sun20i-d1-mmc";
			reg = <0x04020000 0x1000>;
			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
			clock-names = "ahb", "mmc";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			pinctrl-names = "default";
			pinctrl-0 = <&mmc0_pins>;
			max-frequency = <200000000>;
			cap-sd-highspeed;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		r_ccu: clock-controller@7010000 {
			compatible = "allwinner,sun60i-a733-r-ccu";
			reg = <0x07010000 0x230>;
			clocks = <&hosc>, <&rtc CLK_OSC32K>,
				 <&rtc CLK_IOSC>, <&ccu CLK_SYS_24M>,
				 <&ccu CLK_PLL_PERIPH0_200M>,
				 <&ccu CLK_PLL_PERIPH0_300M>,
				 <&ccu CLK_PLL_PERIPH1_300M>;
			clock-names = "hosc", "losc", "iosc", "sys-24m",
				      "pll-periph0-200m", "pll-periph0-300m",
				      "pll-periph1-300m";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc: rtc@7090000 {
			compatible = "allwinner,sun60i-a733-rtc",
				     "allwinner,sun50i-r329-rtc";
			reg = <0x07090000 0x400>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&r_ccu CLK_BUS_R_RTC>, <&hosc>,
				 <&r_ccu CLK_R_AHB>;
			clock-names = "bus", "hosc", "ahb";
			#clock-cells = <1>;
		};
	};
};