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From: Xilin Wu <sophon@radxa.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	 Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>,
	 Rob Clark <robin.clark@oss.qualcomm.com>,
	 Dmitry Baryshkov <lumag@kernel.org>,
	 Abhinav Kumar <abhinav.kumar@linux.dev>,
	 Jessica Zhang <jesszhan0024@gmail.com>,
	Sean Paul <sean@poorly.run>,
	 Marijn Suijten <marijn.suijten@somainline.org>
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	 linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
	 Xilin Wu <sophon@radxa.com>
Subject: [PATCH 07/13] drm/msm/dp: Track validity of cached sink link capabilities
Date: Wed, 30 Sep 2026 20:41:51 +0800	[thread overview]
Message-ID: <20260930-msm-dp-hdr10-v1-7-dbbf8b2b42bc@radxa.com> (raw)
In-Reply-To: <20260930-msm-dp-hdr10-v1-0-dbbf8b2b42bc@radxa.com>

An eDP panel may not have been powered up when its mode is checked, and a
disconnected DP sink can leave cached link capabilities behind. The cached
values alone do not distinguish either case from a current read.

Track whether link capability discovery completed successfully. Clear the
flag before reading capabilities and on unplug, and set it only after the
downstream information has been read successfully. Subsequent atomic
checks can then defer checks against unknown capabilities until the sink
is accessible.

Assisted-by: LLM
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 drivers/gpu/drm/msm/dp/dp_display.c | 1 +
 drivers/gpu/drm/msm/dp/dp_panel.c   | 3 +++
 drivers/gpu/drm/msm/dp/dp_panel.h   | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 1bfa6696d904..9c5b1cd200f8 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -519,6 +519,7 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp)
 			dp->msm_dp_display.connector_type,
 			dp->link->sink_count);
 
+	dp->panel->link_caps_valid = false;
 	if (!dp->plugged)
 		return 0;
 
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index fdf1a3f437ba..f7aac0d25c87 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -247,6 +247,7 @@ int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel,
 
 	panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
 
+	msm_dp_panel->link_caps_valid = false;
 	rc = msm_dp_panel_read_dpcd(msm_dp_panel);
 	if (rc) {
 		DRM_ERROR("read dpcd failed %d\n", rc);
@@ -272,6 +273,8 @@ int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel,
 
 	rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd,
 					 msm_dp_panel->downstream_ports);
+	if (!rc)
+		msm_dp_panel->link_caps_valid = true;
 	return rc;
 }
 
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index 4519ac374220..4fe6af8b304e 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -38,6 +38,7 @@ struct msm_dp_panel {
 	struct msm_dp_panel_psr psr_cap;
 	bool video_test;
 	bool vsc_sdp_supported;
+	bool link_caps_valid;
 	u32 hw_revision;
 
 	u32 max_bw_code;

-- 
2.55.0


  parent reply	other threads:[~2026-09-30 12:43 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-30 12:41 [PATCH 00/13] drm/msm/dp: Add static HDR support for DP and eDP Xilin Wu
2026-09-30 12:41 ` [PATCH 01/13] drm/atomic: Handle max bpc properties before connector state allocation Xilin Wu
2026-09-30 13:26   ` Dmitry Baryshkov
2026-09-30 14:16     ` Xilin Wu
2026-10-01  9:07   ` Maxime Ripard
2026-09-30 12:41 ` [PATCH 02/13] drm/msm/dp: Support multiple generic SDP slots Xilin Wu
2026-09-30 16:05   ` Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 03/13] drm/msm/dp: Track PHY power ownership Xilin Wu
2026-09-30 12:41 ` [PATCH 04/13] drm/msm/dp: Serialize HPD state updates Xilin Wu
2026-09-30 16:07   ` Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 05/13] drm/msm/dp: Unwind resources when enabling a stream fails Xilin Wu
2026-09-30 12:41 ` [PATCH 06/13] drm/msm/dp: Report stream enable failures through link status Xilin Wu
2026-09-30 16:11   ` Dmitry Baryshkov
2026-09-30 12:41 ` Xilin Wu [this message]
2026-09-30 16:14   ` [PATCH 07/13] drm/msm/dp: Track validity of cached sink link capabilities Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 08/13] drm/msm/dp: Rebuild the eDP stream on modesets leaving self refresh Xilin Wu
2026-09-30 12:41 ` [PATCH 09/13] drm/msm/dp: Track output bit depth in bridge atomic state Xilin Wu
2026-09-30 18:05   ` Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 10/13] drm/msm/dp: Signal BT.2020 RGB on DP and eDP Xilin Wu
2026-09-30 18:50   ` Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 11/13] drm/msm/dp: Initialize the debugfs connector pointer Xilin Wu
2026-09-30 18:51   ` Dmitry Baryshkov
2026-09-30 12:41 ` [PATCH 12/13] drm/msm/dp: Serialize video test state changes Xilin Wu
2026-09-30 12:41 ` [PATCH 13/13] drm/msm/dp: Add static HDR metadata support for DP and eDP Xilin Wu
2026-09-30 18:54   ` Dmitry Baryshkov
2026-10-03  0:46 ` [PATCH 00/13] drm/msm/dp: Add static HDR " Dmitry Baryshkov

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