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Mon, 5 Oct 2026 14:25:00 +0000 From: "Peng Fan (OSS)" Date: Mon, 05 Oct 2026 22:21:30 +0800 Subject: [PATCH v2 9/9] gpio: mxc: use BIT() macro for single-bit operations Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261005-gpio-mxc-cleanup-v2-9-bdc3afbb35e2@nxp.com> References: <20261005-gpio-mxc-cleanup-v2-0-bdc3afbb35e2@nxp.com> In-Reply-To: <20261005-gpio-mxc-cleanup-v2-0-bdc3afbb35e2@nxp.com> To: Linus Walleij , Bartosz Golaszewski , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shenwei Wang , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan X-Mailer: b4 0.15.2 X-ClientProxiedBy: SI2PR02CA0047.apcprd02.prod.outlook.com (2603:1096:4:196::14) To AM8PR04MB7874.eurprd04.prod.outlook.com (2603:10a6:20b:24d::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM8PR04MB7874:EE_|GV1PR04MB9198:EE_ X-MS-Office365-Filtering-Correlation-Id: cce5bb4c-7382-4139-1a25-08df22ec705a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|366016|1800799024|7416014|376014|19092799006|56012099006|11063799006|10067099003|6133799003|22082099003|18002099003; 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No functional change. Signed-off-by: Peng Fan --- drivers/gpio/gpio-mxc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c267727061fc..dd6c2e632a42 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -209,7 +209,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) int edge; void __iomem *reg = port->base; - port->both_edges &= ~(1 << gpio_idx); + port->both_edges &= ~BIT(gpio_idx); switch (type) { case IRQ_TYPE_EDGE_RISING: edge = GPIO_INT_RISE_EDGE; @@ -229,7 +229,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) edge = GPIO_INT_HIGH_LEV; pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); } - port->both_edges |= 1 << gpio_idx; + port->both_edges |= BIT(gpio_idx); } break; case IRQ_TYPE_LEVEL_LOW: @@ -246,10 +246,10 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) if (GPIO_EDGE_SEL >= 0) { val = readl(port->base + GPIO_EDGE_SEL); if (edge == GPIO_INT_BOTH_EDGES) - writel(val | (1 << gpio_idx), + writel(val | BIT(gpio_idx), port->base + GPIO_EDGE_SEL); else - writel(val & ~(1 << gpio_idx), + writel(val & ~BIT(gpio_idx), port->base + GPIO_EDGE_SEL); } @@ -259,7 +259,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(val | field_prep(MXC_ICR_MASK(gpio_idx), edge), reg); } - writel(1 << gpio_idx, port->base + GPIO_ISR); + writel(BIT(gpio_idx), port->base + GPIO_ISR); port->pad_type[gpio_idx] = type; } @@ -298,12 +298,12 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) while (irq_stat != 0) { int irqoffset = fls(irq_stat) - 1; - if (port->both_edges & (1 << irqoffset)) + if (port->both_edges & BIT(irqoffset)) mxc_flip_edge(port, irqoffset); generic_handle_domain_irq(port->domain, irqoffset); - irq_stat &= ~(1 << irqoffset); + irq_stat &= ~BIT(irqoffset); } } -- 2.51.0