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Mon, 5 Oct 2026 07:52:48 +0000 (GMT) Received: from fedora (unknown [9.5.7.39]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTPS; Mon, 5 Oct 2026 07:52:47 +0000 (GMT) Date: Mon, 5 Oct 2026 13:30:59 +0530 From: Amit Machhiwal To: Gautam Menghani Cc: maddy@linux.ibm.com, npiggin@gmail.com, mpe@ellerman.id.au, chleroy@kernel.org, ritesh.list@gmail.com, sshegde@linux.ibm.com, nnmlinux@linux.ibm.com, amachhiw@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Timothy Pearson Subject: Re: [PATCH v3] KVM: PPC: Book3S HV: Avoid spurious interrupts caused by LPCR_MER bit Message-ID: <20261005131832.8f6b2b14-d5-amachhiw@linux.ibm.com> Mail-Followup-To: Gautam Menghani , maddy@linux.ibm.com, npiggin@gmail.com, mpe@ellerman.id.au, chleroy@kernel.org, ritesh.list@gmail.com, sshegde@linux.ibm.com, nnmlinux@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Timothy Pearson References: <20260921111043.49825-1-gautam@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260921111043.49825-1-gautam@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=TOPQ2Fla c=1 sm=1 tr=0 ts=6ac35758 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VwQbUJbxAAAA:8 a=yKAn6K1XAAAA:8 a=_AprYWD3AAAA:8 a=VnNF1IyMAAAA:8 a=EThlqOoKbmT7VKALfbcA:9 a=CjuIK1q_8ugA:10 a=6M1ixcW_PCWoKiWyFx5v:22 a=fKH2wJO7VO9AkD4yHysb:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA1MDAzMCBTYWx0ZWRfX2InbMOps9S09 JI+jwuFS/ZBJCj7AAFdKAc8Wis3oh+tm2iyOkkOBXYk5rOsUx4OPGw6qD98MbVu0I5Oo/dVfLNC rfMKo7sN31SO7dEBQmfK5c1yEy1WGXKPgzdIHwGEzMwmvYFh30YdUB7JrzjleyCD/Kc54Wl1t4+ NOCUjRVZFeS+3jwuIujjxRkxPyXJg5JYqHLM6X4TJpOi1ztnoujWXPyHcfqsZRlzNkaH3N+nPqk tDa6zEK+ZPCGp9t2em/YmPqWL9gQwmHXQ4tw48Ldw67mCjI+ofPc53DUQatEzJOFH/pPbWnNpC+ vU6s0sZTZeX7W2mFA1nMOjJD+8DVJdbxNLlFzGR19LRrMocxYKdlPLntstwDDyZ9BQBudjE5QxQ UK8yD2/gXh+hiQUICAn3IcrKxejyyM9AEg38XpUSDmovniqVUuAUY3Vog0lQWHP9VSZ4ofeBzVr NulN/EI6QqioziJ8wLA== X-Proofpoint-GUID: z3VeellNhN-20HClfkBmum5rlFaw0hFJ X-Proofpoint-ORIG-GUID: is6NVzq44xhVgSXksG9snG8P5amf8ebg X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA1MDAzMCBTYWx0ZWRfX6INeK+u8IbeW 9yV2bMXqmwIx1n4til78OiMAuYtKetphFSAXcTv7HLO3RKb5DTu9ZhDkxNq+hNIvwJX6s3B+WCv OkDWbsYrtFWXHmIX2XBrql0x+PmqUFU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-05_01,2026-10-02_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610050030 Hi Gautam, Thanks for the patch and working on this. I have a couple of questions though. On 2026/09/21 04:40 PM, Gautam Menghani wrote: > A huge number of spurious interrupts can be seen immediately after a KVM > on PowerNV guest boots up in XIVE mode. > > $ cat /proc/interrupts | grep SPU > SPU: 223705 192439 273526 147623 Spurious interrupts > > This bug was introduced by commit ecd10702baae5 ("KVM: PPC: Book3S HV: > Handle pending exceptions on guest entry with MSR_EE"). The root cause > is that once LPCR_MER bit is set, it is supposed to be reset by > software. But when a vCPU starts running with LPCR_MER set, the vCPU does > not exit back to the host until the decrementer expires or there is an > hcall, etc. This is because KVM on PowerNV guests have support for > native XIVE, so they are not dependent on host for interrupt emulation. > Due to this behaviour, a huge number of spurious interrupts are seen > since LPCR_MER continues to be set and LPCR_MER cannot be reset until the > vCPU exits to the host. > > Fix this behaviour by not using the LPCR_MER bit whenever native XIVE is > available (currently in case of KVM on PowerNV only), as the XIVE hardware > can present interrupts to the KVM guest vCPU directly. So the LPCR_MER > functionality is not required. This reduces the number of spurious > interrupts drastically. > > Fixes: ecd10702baae5 ("KVM: PPC: Book3S HV: Handle pending exceptions on guest entry with MSR_EE") > Cc: stable@vger.kernel.org # 6.8+ > Reported-by: Timothy Pearson > Closes: https://lore.kernel.org/linuxppc-dev/582904882.11159.1786719390349.JavaMail.zimbra@raptorengineeringinc.com > Signed-off-by: Gautam Menghani > --- > v3: > 1. Continue the use of LPCR_MER when kernel-irqchip=off (Sashiko) > > v2: > 1. Handle the case where xive_interrupt_pending() is true and also the > external exception bit is set. (Narayana) > > arch/powerpc/include/asm/kvm_ppc.h | 7 +++++++ > arch/powerpc/kvm/book3s_hv.c | 2 +- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h > index 169ea6a7fbad..580ad2548c2b 100644 > --- a/arch/powerpc/include/asm/kvm_ppc.h > +++ b/arch/powerpc/include/asm/kvm_ppc.h > @@ -747,6 +747,11 @@ static inline int kvmppc_xive_enabled(struct kvm_vcpu *vcpu) > return vcpu->arch.irq_type == KVMPPC_IRQ_XIVE; > } > > +static inline bool kvmppc_xive_native_enabled(struct kvm *kvm) > +{ > + return kvm->arch.xive_devices.native; > +} > + > extern int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev, > struct kvm_vcpu *vcpu, u32 cpu); > extern void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu); > @@ -782,6 +787,8 @@ static inline bool kvmppc_xive_rearm_escalation(struct kvm_vcpu *vcpu) { return > > static inline int kvmppc_xive_enabled(struct kvm_vcpu *vcpu) > { return 0; } > +static inline bool kvmppc_xive_native_enabled(struct kvm *kvm) { return false; } > + > static inline int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev, > struct kvm_vcpu *vcpu, u32 cpu) { return -EBUSY; } > static inline void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu) { } > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index dbac3573b2c8..cb2bb29451a7 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -4980,7 +4980,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit, > if (!kvmhv_on_pseries() && (__kvmppc_get_msr_hv(vcpu) & MSR_EE)) > kvmppc_inject_interrupt_hv(vcpu, > BOOK3S_INTERRUPT_EXTERNAL, 0); > - else > + else if (!kvmppc_xive_native_enabled(vcpu->kvm)) > lpcr |= LPCR_MER; 1. What happens when an L1 KVM guest is booted with (native) XIVE and then the guest is rebooted with `xive=off` i.e., with XICS? Will we stop setting LPCR_MER as kvm->arch.xive_devices.native would still be set? 2. What happends when an L1 KVM guest is booted with XIVE and then we kexec into a new kernel with `xive=off`? You did mention in your other reply that with kexec, `xive=off` is ignored currently but IMO, we would want to understand where this limiation lies and fix that if need be. I do understand we are trying to fix spurious interrupts problem with XIVE in this patch and this particular problem can be taken separately but it worth investigating. Thanks, Amit