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Tue, 06 Oct 2026 07:04:25 -0700 (PDT) From: Matt Turner Date: Tue, 06 Oct 2026 10:04:16 -0400 Subject: [PATCH 4/6] alpha: define granularity hint PTE bits Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261006-alpha-hugepages-v1-4-a673a18aaa70@gmail.com> References: <20261006-alpha-hugepages-v1-0-a673a18aaa70@gmail.com> In-Reply-To: <20261006-alpha-hugepages-v1-0-a673a18aaa70@gmail.com> To: Richard Henderson , Magnus Lindholm Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, Matt Turner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4281; i=mattst88@gmail.com; h=from:subject:message-id; bh=rggXStTfISGZMrfhil87y009ll/LlVaJhKCPzwrTe4Q=; b=owGbwMvMwCW25rVmCc8sv+mMp9WSGLKO/L/79M8ikyUTDW+v+ld4/rurbm7U/vlaSitPW6h7v dLTyD5r2vGBhUGMi2GmmCJL3HpFllltO5b6nJb+BTOHlQlkiLRIAwMQsDDw5SbmlRrpGOmZahvq GQIZOkbxEDk9Bo3M4uLS1CLdtIIih7z8ksSSzPy8Yr38gtS8gvQCvbTMtJKMjPyi4lSgEXp5qSW mro5uRoYGJpaOFmZOFo6mJs7OToZObo6Ozq5ORpbmJgbOlo4mrpbmDFycAjDXZH5iZNhd5aC6yf GhRdv0FRsPMgSLpFUIiQjcb1HuO+Ay867u1RkMP75N7/qcc/zWtror3XGPeudufqORnru5y8LRy Ocv50cWFgA= X-Developer-Key: i=mattst88@gmail.com; a=openpgp; fpr=3BB639E56F861FA2E86505690FDD682D974CA72A Bits <6:5> of the Alpha PTE are the granularity hint, described in Table 17-3 of the Alpha Architecture Reference Manual. A hint of N marks the PTE as one of a block of 8^N physically contiguous, naturally aligned pages that the translation buffer may map with a single entry. With 8KB pages that gives 64KB, 512KB and 4MB blocks. Define the field and the helpers to encode and decode it. Nothing sets a non-zero hint yet. Add the hint to _PAGE_CHG_MASK so that pte_modify() preserves it. Swap PTEs leave bits <31:0> clear, so pte_huge() is false on swap, migration and marker entries, and page table entries above the last level keep a zero hint where pmd_bad() would reject anything else. Signed-off-by: Matt Turner --- arch/alpha/include/asm/pgtable.h | 51 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index d123fd0d4091..605b82f73a98 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h @@ -65,6 +65,8 @@ struct vm_area_struct; #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */ #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */ #define _PAGE_ASM 0x0010 +#define _PAGE_GH_MASK 0x0060 /* granularity hint, PTE<6:5> */ +#define _PAGE_GH_SHIFT 5 /* * The Alpha AXP ARM defines 8 protection bits in PTE[15:8]: KRE, ERE, SRE, * URE, KWE, EWE, SWE, UWE (Kernel/Executive/Supervisor/User Read/Write @@ -103,7 +105,36 @@ struct vm_area_struct; #define _PFN_MASK 0xFFFFFFFF00000000UL #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS) -#define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS | _PAGE_SPECIAL) +/* + * pte_modify() must preserve the granularity hint, or + * hugetlb_change_protection() would turn a block into single-page PTEs. + */ +#define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS | \ + _PAGE_GH_MASK | _PAGE_SPECIAL) + +/* + * Granularity hints. A PTE with hint order N is one of a block of 8^N + * physically contiguous pages, naturally aligned both virtually and + * physically, that the TB may map with a single entry. With 8KB pages the + * four encodings give 8KB, 64KB, 512KB and 4MB. + * + * Every PTE of a block must still carry the PFN of its own page, and all of + * them must agree in bits <15:0>: the protection, fault, hint and valid bits. + * __ACCESS_BITS and __DIRTY_BITS reach into that range, so young and dirty + * updates have to be applied to the whole block too. + * + * The hint is advisory: an implementation that ignores it still translates + * correctly through the individual PTEs, so it is safe to set on any Alpha. + */ +#define GH_ORDER_MAX 4 /* hint orders 0..3 */ + +#define gh_cont_shift(order) (PAGE_SHIFT + 3 * (order)) +#define gh_cont_size(order) (1UL << gh_cont_shift(order)) +#define gh_cont_mask(order) (~(gh_cont_size(order) - 1)) +#define gh_pte_num(order) (1UL << (3 * (order))) + +#define for_each_gh_order(order) \ + for ((order) = 1; (order) < GH_ORDER_MAX; (order)++) /* * All the normal masks have the "page accessed" bits on, as any time they are used, @@ -269,6 +300,24 @@ extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; retu extern inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } extern inline pte_t pte_mkspecial(pte_t pte) { pte_val(pte) |= _PAGE_SPECIAL; return pte; } +extern inline unsigned int pte_gh_order(pte_t pte) +{ + return (pte_val(pte) & _PAGE_GH_MASK) >> _PAGE_GH_SHIFT; +} + +extern inline pte_t pte_mkgh(pte_t pte, unsigned int order) +{ + pte_val(pte) &= ~_PAGE_GH_MASK; + pte_val(pte) |= (unsigned long)order << _PAGE_GH_SHIFT; + return pte; +} + +/* + * Swap PTEs leave bits <31:0> clear, so this is false for every swap, + * migration and marker entry, not just for ordinary small pages. + */ +extern inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_GH_MASK; } + /* * The smp_rmb() in the following functions are required to order the load of * *dir (the pointer in the top level page table) with any subsequent load of -- 2.54.0