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Tue, 6 Oct 2026 12:23:16 +0000 From: Laurentiu Palcu To: Ying Liu , Frank Li , Luca Ceresoli , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Laurentiu Palcu , linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v10 3/9] drm/bridge: fsl-ldb: Add support for i.MX94 Date: Tue, 6 Oct 2026 12:21:58 +0000 Message-ID: <20261006-dcif-upstreaming-v10-3-bcfb28de0aae@oss.nxp.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261006-dcif-upstreaming-v10-0-bcfb28de0aae@oss.nxp.com> References: <20261006-dcif-upstreaming-v10-0-bcfb28de0aae@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR3P281CA0069.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:4b::16) To GV2PR04MB12318.eurprd04.prod.outlook.com (2603:10a6:150:32b::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12318:EE_|AS8PR04MB9045:EE_ X-MS-Office365-Filtering-Correlation-Id: 71a3bfda-1125-4251-e7dc-08df23a49981 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|19092799006|366016|7416014|376014|23010399003|921020|11063799006|10067099003|56012099006|18002099003|22082099003; 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Add a 'max_clk_khz' member to the fsl_ldb_devdata structure in order to be able to set different max frequencies for other platforms. Reviewed-by: Frank Li Signed-off-by: Laurentiu Palcu --- drivers/gpu/drm/bridge/fsl-ldb.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index 52ae7f5b63c7c..5da1b2cc9b6cc 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -57,6 +57,7 @@ enum fsl_ldb_devtype { IMX6SX_LDB, IMX8MP_LDB, IMX93_LDB, + IMX94_LDB, }; struct fsl_ldb_devdata { @@ -64,21 +65,31 @@ struct fsl_ldb_devdata { u32 lvds_ctrl; bool lvds_en_bit; bool single_ctrl_reg; + u32 max_clk_khz; }; static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { [IMX6SX_LDB] = { .ldb_ctrl = 0x18, .single_ctrl_reg = true, + .max_clk_khz = 80000, }, [IMX8MP_LDB] = { .ldb_ctrl = 0x5c, .lvds_ctrl = 0x128, + .max_clk_khz = 80000, }, [IMX93_LDB] = { .ldb_ctrl = 0x20, .lvds_ctrl = 0x24, .lvds_en_bit = true, + .max_clk_khz = 80000, + }, + [IMX94_LDB] = { + .ldb_ctrl = 0x04, + .lvds_ctrl = 0x08, + .lvds_en_bit = true, + .max_clk_khz = 148500, }, }; @@ -274,7 +285,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) + if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 2 : 1) * fsl_ldb->devdata->max_clk_khz) return MODE_CLOCK_HIGH; return MODE_OK; @@ -386,6 +397,8 @@ static const struct of_device_id fsl_ldb_match[] = { .data = &fsl_ldb_devdata[IMX8MP_LDB], }, { .compatible = "fsl,imx93-ldb", .data = &fsl_ldb_devdata[IMX93_LDB], }, + { .compatible = "fsl,imx94-ldb", + .data = &fsl_ldb_devdata[IMX94_LDB], }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, fsl_ldb_match); -- 2.53.0