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Tue, 6 Oct 2026 12:23:29 +0000 From: Laurentiu Palcu To: Ying Liu , Frank Li , Luca Ceresoli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: Laurentiu Palcu , linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v10 7/9] arm64: dts: imx94: Add display pipeline nodes Date: Tue, 6 Oct 2026 12:22:02 +0000 Message-ID: <20261006-dcif-upstreaming-v10-7-bcfb28de0aae@oss.nxp.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261006-dcif-upstreaming-v10-0-bcfb28de0aae@oss.nxp.com> References: <20261006-dcif-upstreaming-v10-0-bcfb28de0aae@oss.nxp.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: FR3P281CA0181.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:a4::14) To GV2PR04MB12318.eurprd04.prod.outlook.com (2603:10a6:150:32b::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB12318:EE_|DU4PR04MB10742:EE_ X-MS-Office365-Filtering-Correlation-Id: f1391bc3-ad4c-4b95-71be-08df23a4a076 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|19092799006|366016|7416014|376014|18002099003|22082099003|921020|10067099003|3023799007|56012099006|11063799006; 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* clock-ldb-pll-div7 needed by DCIF and LDB; * Display controller interface (DCIF); * LVDS display bridge (LDB); Co-developed-by: Peng Fan Signed-off-by: Peng Fan Signed-off-by: Laurentiu Palcu --- arch/arm64/boot/dts/freescale/imx94.dtsi | 82 ++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 020aa1da33150..98b8cf5eb2ab3 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -3,6 +3,7 @@ * Copyright 2024-2025 NXP */ +#include #include #include #include @@ -39,6 +40,15 @@ clk_ext1: clock-ext1 { clock-output-names = "clk_ext1"; }; + clk_ldb_pll_div7: clock-ldb-pll-div7 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_LDBPLL>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "ldb_pll_div7"; + }; + sai1_mclk: clock-sai1-mclk1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1312,6 +1322,78 @@ wdog4: watchdog@49230000 { }; }; + dispmix_csr: syscon@4b010000 { + compatible = "nxp,imx94-display-csr", "syscon"; + reg = <0x0 0x4b010000 0x0 0x10000>; + clocks = <&scmi_clk IMX94_CLK_DISPAPB>; + #clock-cells = <1>; + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>; + assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>, + <&scmi_clk IMX94_CLK_DISPAPB>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333333>; + }; + + lvds_csr: syscon@4b0c0000 { + compatible = "nxp,imx94-lvds-csr", "syscon"; + reg = <0x0 0x4b0c0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&scmi_clk IMX94_CLK_DISPAPB>; + #clock-cells = <1>; + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>; + + ldb: ldb@4 { + compatible = "fsl,imx94-ldb"; + reg = <0x4 0x4>, <0x8 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>; + clock-names = "ldb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in: endpoint { + remote-endpoint = <&dcif_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + }; + + dcif: display-controller@4b120000 { + compatible = "nxp,imx94-dcif"; + reg = <0x0 0x4b120000 0x0 0x300000>; + interrupts = , + , + ; + interrupt-names = "common", "bg_layer", "fg_layer"; + clocks = <&scmi_clk IMX94_CLK_DISPAPB>, + <&scmi_clk IMX94_CLK_DISPAXI>, + <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>; + clock-names = "apb", "axi", "pix"; + assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>; + assigned-clock-parents = <&clk_ldb_pll_div7>; + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>; + status = "disabled"; + + port { + dcif_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; + }; + hsio_blk_ctl: syscon@4c0100c0 { compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; reg = <0x0 0x4c0100c0 0x0 0x1>; -- 2.53.0