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Mon, 02 Nov 2026 05:57:01 -0800 (PST) Received: from [127.0.0.1] ([64.43.42.35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4abe77053fesm126145375e9.0.2026.11.02.05.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 05:57:01 -0800 (PST) From: bryan.odonoghue@linaro.org X-Google-Original-From: bod@kernel.org Date: Mon, 02 Nov 2026 13:56:50 +0000 Subject: [PATCH v2 4/9] media: qcom: camss: csid-gen3: Enable RDI SOF driving X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261102-v4l2-frame-sync-v2-4-25cbed7a772f@kernel.org> References: <20261102-v4l2-frame-sync-v2-0-25cbed7a772f@kernel.org> In-Reply-To: <20261102-v4l2-frame-sync-v2-0-25cbed7a772f@kernel.org> To: Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A From: Bryan O'Donoghue Add in silicon enabling code to generate SOF and trigger the routine which produces V4L2_EVENT_FRAME_SYNC based on SOF per standard v4l2 behaviour. Signed-off-by: Bryan O'Donoghue --- .../media/platform/qcom/camss/camss-csid-gen3.c | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c index 0fdbf75fb27db..6a538d825f78b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -34,6 +34,7 @@ #define CSID_RUP_AUP_RDI(rdi) ((BIT(4) | BIT(20)) << (rdi)) #define CSID_TOP_IRQ_STATUS 0x7C +#define TOP_IRQ_RDI(rdi) BIT(8 + (rdi)) #define TOP_IRQ_STATUS_RESET_DONE BIT(0) #define CSID_TOP_IRQ_MASK 0x80 @@ -58,6 +59,9 @@ #define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0xEC + 0x10 * (rdi)) #define RUP_DONE_IRQ_STATUS BIT(23) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0xF0 + 0x10 * (rdi)) +#define INFO_INPUT_SOF_IRQ BIT(12) + #define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0xF4 + 0x10 * (rdi)) #define CSID_CSI2_RDIN_IRQ_SET(rdi) (0xF8 + 0x10 * (rdi)) @@ -219,6 +223,25 @@ static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 writel(val, csid->base + CSID_RDI_CFG0(port)); } +static void __csid_configure_rdi_irq(struct csid_device *csid, u8 enable, u8 rdi) +{ + u32 val = 0; + + if (enable) + val = INFO_INPUT_SOF_IRQ; + + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_MASK(rdi)); + + val = readl(csid->base + CSID_TOP_IRQ_MASK); + + if (enable) + val |= TOP_IRQ_RDI(rdi); + else + val &= ~TOP_IRQ_RDI(rdi); + + writel(val, csid->base + CSID_TOP_IRQ_MASK); +} + static void csid_configure_stream(struct csid_device *csid, u8 enable) { u8 i; @@ -230,6 +253,7 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) if (csid->phy.en_vc & BIT(i)) { __csid_configure_rdi_stream(csid, enable, i, 0); __csid_configure_rx(csid, &csid->phy, 0); + __csid_configure_rdi_irq(csid, enable, i); __csid_ctrl_rdi(csid, enable, i); } } @@ -279,6 +303,9 @@ static irqreturn_t csid_isr(int irq, void *dev) val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + if (val & INFO_INPUT_SOF_IRQ) + csid_sof_event(csid, i); + if (val & RUP_DONE_IRQ_STATUS) /* clear the reg update bit */ csid_subdev_reg_update(csid, i, true); -- 2.56.0