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Mon, 18 May 2026 20:39:41 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , Shuai Xue Subject: [PATCH v4 15/24] iommu/arm-smmu-v3: Co-clear pending CMDQ_ERR when CMD_SYNC times out Date: Mon, 18 May 2026 20:38:58 -0700 Message-ID: <31fddf88d78e830a7cfd407d44c15c0c536fd0d6.1779161849.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C8:EE_|DM4PR12MB8449:EE_ X-MS-Office365-Filtering-Correlation-Id: b96fb4f7-9ab3-43cb-01e5-08deb5584ad3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|22082099003|18002099003|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: LxyfaRP8xDCwGp1UxNGPPp9IKnM8LjMsh/za9mmwJQhMu9oMo1TFbdig6ki/v2qhcPLTPTOYQ+To2Tld9NxBQCcGgPigH2D3dgW4r8fs9ImbrDqEy+z0jvMoku4Jtzs0Yr49Fut+49cqXG8Z8OwM6SGYrNxEMdt7sG1xU/sM0B9y0JuRX7IHrVnTMPEtN451ibUngZmaw//JiW/LBKYb2tnY3qLGWkFqPRckFdPMpGpxRhwa09PITGwL4BVgd8SBfjvWYnFJdR+asiPAi1JXuEki/OCQHnGI2wS01jOlR2F4a0bz3oRMugpceMlpgxWXy/qLDcsVq/E6KJ3ziGO7E9soR4KHCdGFVT41oCrckNEhoPYaShM45vIW+Z+WfkD6KFK1SGFrp//o4Xo9+B+lWZSUtsDnuDQUCv0Jf0w1MJLiHaY0/VU3vcU6Sd6gG/pYJUp2m5B8xqZtv/RgiZXtDyjhPatRoCaxoZygc2ZBjY8etwwzdRcQOLOEQKvxGAWccxAlbIK1EGCFT6e2/lplQEjtWb+aMLfQrUHXpN43rdUZIP/+GUWaNAkc8QN3iwxRApKNxEtvWjeBu9oYEHJB0qUbmpwbuSti9Y/mBxUiAq194VpyLW1a5J2GO2HQymN3RK7w3J+++qm48iZWPNP8k+YB9ljXK9QoUVgtkKFyI201mJF6b+tE7Cd32haXUrB5I7YJEQze5whZf3uXxIqYY85l2Mp0i3Lu/KfYPNjWLak= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(22082099003)(18002099003)(56012099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xb4KwECbP/3cl4R6La3ttOK7pdJXpf/308jsgFYW1Q8UQJ2g+YBfugvMPYy1Rl6gn2I2v2MrDuOgNKHFGXCwPSkxeOVv9EQ4dRiF4GH0NPbba5N76vDAFkF543FgXBK/ljZub0kTRZS/2etSmYRenvxwVdBqUGhxxraWPDHYlvwTwpUs4Qt2Q52EzaBZpnjoX9GQQ3CEoiEQ/0TtZ72QPLqBJspyNqQHO0VcihHuaQVebky1aqSQEoAFIIM6k0wwbdDCqKQAs60Y3tnXYtXT5cE3ltAc5CH3+MQ6fEPwwp4SHTJ2HzeQb1qdh2eeKYJ2R3lyruncJMH+uCmfAq2lDZcscf7w1OphNamUaELZ8OI8pG5sz3dvfhJwZS3MWOpfbtlDDZM3/mt6fWDKpEDgkmfoGjFTTnen5SKTEK/LUOY6qvBBtkdDd3iIxa69dDPm X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 03:39:54.8835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b96fb4f7-9ab3-43cb-01e5-08deb5584ad3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8449 Once arm_smmu_cmdq_poll_until_sync() returns, arm_smmu_cmdq_issue_cmdlist() tests its CMD_SYNC slot in atc_sync_timeouts to decide whether there was an ATC_INV timeout. On the other hand, when that poll timed out, the GERROR ISR might have been delayed past the poll deadline, so the atc_sync_timeouts test could miss an ATC_INV timeout, classifying it as a generic CMD_SYNC timeout and bypassing the per-device quarantine. Add two cmdq_err_handler impl functions: - arm_smmu_cmdq_err_handler() reads SMMU GERROR/GERRORN. - tegra241_vcmdq_handle_cmdq_err() reads VCMDQ GERROR/GERRORN. Co-clear any pending CMDQ_ERR in the issuer, when the polling on a CMD_SYNC times out. Each cmdq impl serializes the synchronous drain against its own IRQ handler with cmdq->cmdq_err_lock. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++++++++++++- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 23 +++++++++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index fc0757359b783..7f81fd2e92480 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -813,6 +813,15 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, sync_prod = llq.prod; ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); + /* + * When the poll above timed out, the GERROR ISR might have been + * delayed past the poll deadline, so the atc_sync_timeouts test + * below could miss our ATC_INV timeout. Thus, drain any pending + * CMDQ_ERR synchronously first via the per-cmdq callback. + */ + if (ret && cmdq->cmdq_err_handler) + cmdq->cmdq_err_handler(smmu, cmdq); + /* * Test atc_sync_timeouts first and see if there is ATC timeout * resulted from this cmdlist. Return -EIO to separate from the @@ -2251,6 +2260,31 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) static int arm_smmu_device_disable(struct arm_smmu_device *smmu); +/* + * Drain a pending CMDQ_ERR on the primary cmdq. Installed as the primary + * cmdq's cmdq_err_handler so arm_smmu_cmdq_issue_cmdlist() can drain after + * a CMD_SYNC poll timeout; serialized against arm_smmu_gerror_handler() by + * cmdq->cmdq_err_lock. + */ +static void arm_smmu_cmdq_err_handler(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + u32 gerror, gerrorn; + + guard(raw_spinlock_irqsave)(&cmdq->cmdq_err_lock); + + gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); + gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); + + if (!((gerror ^ gerrorn) & GERROR_CMDQ_ERR)) + return; + + __arm_smmu_cmdq_skip_err(smmu, cmdq); + + /* Toggle only the CMDQ_ERR bit; other bits are left for the ISR. */ + writel(gerrorn ^ GERROR_CMDQ_ERR, smmu->base + ARM_SMMU_GERRORN); +} + static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) { u32 gerror, gerrorn, active; @@ -4399,7 +4433,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq, NULL); + ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq, arm_smmu_cmdq_err_handler); if (ret) return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index fb2f8f68fa344..e04107f0490c9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -337,6 +337,27 @@ static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) } } +static void tegra241_vcmdq_handle_cmdq_err(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + struct tegra241_vcmdq *vcmdq = + container_of(cmdq, struct tegra241_vcmdq, cmdq); + u32 gerror, gerrorn; + + guard(raw_spinlock_irqsave)(&cmdq->cmdq_err_lock); + + gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)); + gerrorn = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + + if (!((gerror ^ gerrorn) & GERROR_CMDQ_ERR)) + return; + + __arm_smmu_cmdq_skip_err(smmu, cmdq); + + /* Toggle only the CMDQ_ERR bit on this VCMDQ's GERRORN */ + writel(gerrorn ^ GERROR_CMDQ_ERR, REG_VCMDQ_PAGE0(vcmdq, GERRORN)); +} + static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) { struct tegra241_cmdqv *cmdqv = (struct tegra241_cmdqv *)devid; @@ -652,7 +673,7 @@ static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq) q->q_base = q->base_dma & VCMDQ_ADDR; q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift); - return arm_smmu_cmdq_init(smmu, cmdq, NULL); + return arm_smmu_cmdq_init(smmu, cmdq, tegra241_vcmdq_handle_cmdq_err); } /* VINTF Logical VCMDQ Resource Helpers */ -- 2.43.0