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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA0NyBTYWx0ZWRfX43jXsnqeFivk XZls/Qq1mVzkSX8hLNyAiVE5IOAsID4/2Qupw9KMTBFONLzywTJzTgCT+WAL28h3E9Odc62uZIY FxXHlLC9OQa4YzYZPZmRsfZ6q06RRQA= X-Proofpoint-GUID: SgBnty9FwuvXZkYrETRuDx3R-8RgIsck X-Authority-Analysis: v=2.4 cv=W9GtxhWk c=1 sm=1 tr=0 ts=6abcf8e4 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=H9QmddT51QaNM9ltfMQA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA0NyBTYWx0ZWRfX1ODDfEfAv+cW dLtpP0RlMEsvqLC2PgTm7Y+esj2/SBJIxlXirVmoMlTu7EwXAs4xQ1jk4rzHeEtxQ36HXOhKvN9 RzsmA/UggdEUL9UxGgKrXGh2Vh9OM8KrQCGoe2aV74aS6F4H1BQRtlm49gvGQjU55tUDsE2QqSo 4gYSK5C0nHJ1UvLGwaYylrLUzXRfShLad3myMPakb9ruUCFq+IfGcxgYb7hUwMg4iA3swE7BK0L 4d9KKZjHJU4zm8kCFTsvZt8GEcjJN1OMkSRWpOw7NA02rVxtrkGn7qZQCkELSpTBTk91lClC5Kb bmxqO+vyJrWryslT1jecl4pncL3klccwRyXTxYpCvJtW9IR984GlLzMUqMVfALqCE9wuZ3Ii6zD sN1kz9NCAEheuoJnjALzhtgw8Q34c2APY90avmqUfcMSNZzlnC6S+32bhXr9y2dAckUxqfc4TRo KrcDfMDfQg6mXVT9g3g== X-Proofpoint-ORIG-GUID: SgBnty9FwuvXZkYrETRuDx3R-8RgIsck X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300047 On 9/25/26 10:46 AM, Srinivas Kandagatla wrote: > Add support for the lpass clock controller found on Glymur based devices. > This would allow lpass peripheral loader drivers to control the clocks and > bring the subsystems out of reset. > > Currently this patch only supports resets as the Q6DSP is in control of > LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg > channel. > > Signed-off-by: Srinivas Kandagatla > Reviewed-by: Abel Vesa > --- > drivers/clk/qcom/lpasscc-glymur.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/clk/qcom/lpasscc-glymur.c b/drivers/clk/qcom/lpasscc-glymur.c > index 356625dce99e..eda13686850c 100644 > --- a/drivers/clk/qcom/lpasscc-glymur.c > +++ b/drivers/clk/qcom/lpasscc-glymur.c > @@ -37,10 +37,31 @@ static const struct qcom_cc_desc lpass_audiocc_glymur_reset_desc = { > .num_resets = ARRAY_SIZE(lpass_audiocc_glymur_resets), > }; > > +static const struct qcom_reset_map lpasscc_glymur_resets[] = { > + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa028, 1 }, GPT says this register doesn't exist Konrad