Re: ix86 Atomic ops during DMA...

[Brian Gerst <bgerst@quark.didntduck.org>]

Richard B. Johnson wrote:
> Hello,
> 
> A piece of hardware needs its interrupt status written back
> to its status register to "clear" interrupts and thus enable
> more.. This is in an uninterruptible ISR. This, of course
> can be readily accomplished by using the standard readl() and
> writel() macros.........but! If a DMA is in progress, a hardware
> debugger shows many milliseconds between the read and the write.
> 
> This allows a race condition to exist. So, how do I lock the bus
> during the read and write?  A lock on ix86 locks only the
> next instruction, not the next plus time for another lock
> which appears to be needed.
> 
> 	I need...
> 
> 	movl (%ebx), %eax	# Read status from register in ebx
> 	movl %eax, (%ebx)	# Write it back
> 
> ..to occur together without the bus being taken away by a DMA
>  operation until these two instructions are complete.

You need a single read-modify-write instruction like:

lock orl $0, addr

--
			Brian Gerst