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Signed-off-by: Mahesh Rao Signed-off-by: Tze Yee Ng --- Changes in v3: - Reflow commit message body to ~75 columns (fix Dinh's comment in v2 review) - No functional change - Drop Reviewed-by: Matthew Gerlach (no longer at Altera) - Add Signed-off-by: Tze Yee Ng --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dfbafde8822..3168449dcd3d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -65,6 +65,8 @@ svc { compatible = "intel,agilex-svc"; method = "smc"; memory-region = <&service_reserved>; + interrupts = ; + interrupt-parent = <&intc>; fpga_mgr: fpga-mgr { compatible = "intel,agilex-soc-fpga-mgr"; -- 2.43.7