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charset="utf-8" X-RootMTR: 20260904132708eucas1p1adfa26ef0fe5109eca63a3aeadf74915 X-EPHeader: CA X-CMS-RootMailID: 20260904132708eucas1p1adfa26ef0fe5109eca63a3aeadf74915 References: <20260904-jh7110-clean-send-v3-0-484f9ae72715@samsung.com> On 9/6/26 05:55, Dominique Belhachemi wrote: > On Sat, Sep 5, 2026 at 1:21 AM Maud Spierings > wrote: > >> Hello Michal, >> >> This new version added some more issues on my fml13v01 board, this time >> 2 registers in the VOUT_CRG are misconfigured that were correct in v2, >> namely: >> >> 0x295c0004 was 0x00000004 on the previous version but is now 0x00000006 >> 0x295c001c was 0x81000000 on the previous version but is now 0x80000000 >> >> xx04 sets a slightly different clock divider, but it doesn't seem to >> matter, display also works with this changed value. >> >> xx1c seems to select the wrong clock mux? >> >> After correcting 0x295c001c (and the ones that I mentioned before in the >> hdmitx block), the display comes to life again. >> >> Not sure why these are changed. >> >> Same here on a VisionFive 2. The dc8200_pix0 mux register (0x295c001c) > comes up 0x80000000 instead of 0x81000000 (which selects hdmitx0_pixelclk > from the PHY). > > v3 added CLK_SET_RATE_NO_REPARENT to stop clk_set_rate() from silently > switching which clock feeds the display, but nothing then assigns the > parent, > so it is left on whatever the bootloader selected. > > You could pin the two pixel-clock muxes to the HDMI PHY, is that acceptable? > > dc8200: display@29400000 { > + assigned-clocks = <&voutcrg > JH7110_VOUTCLK_DC8200_PIX0>, > + <&voutcrg > JH7110_VOUTCLK_DC8200_PIX1>; > + assigned-clock-parents = <&hdmi_phy>, > <&hdmi_phy>; > }; > > I tested this on the vf2. Thank you Maud and Dominique, I've tested this as well and it does seem like a good fix, will include this in a v4. > > Best > -Dominique > Best regards, -- Michal Wilczynski