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([2406:b400:b5:60e5:312a:8741:b738:744]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5c05f287sm270216785ad.24.2026.05.19.22.04.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 May 2026 22:04:29 -0700 (PDT) Message-ID: <55470717-3e9e-4548-b12a-8e2a2e1f6c63@oss.qualcomm.com> Date: Wed, 20 May 2026 10:34:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] arm64: dts: qcom: monaco: add AEST error nodes To: Konrad Dybcio , Ruidong Tian , Tony Luck , Borislav Petkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, rafael@kernel.org, mark.rutland@arm.com, Sudeep Holla Cc: linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Faruque Ansari References: <20260505-aest-devicetree-support-v1-0-d5d6ffacf0a5@oss.qualcomm.com> <20260505-aest-devicetree-support-v1-8-d5d6ffacf0a5@oss.qualcomm.com> <71eee892-1c0b-49e7-a82d-9016c56e8592@oss.qualcomm.com> Content-Language: en-US From: Umang Chheda In-Reply-To: <71eee892-1c0b-49e7-a82d-9016c56e8592@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BOCDalQG c=1 sm=1 tr=0 ts=6a0d40df cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=8C-fUGBXRnHmYMWNGq8A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: IkQpl3CShTL8R68XeMxGIYv0U1ojUtVz X-Proofpoint-GUID: IkQpl3CShTL8R68XeMxGIYv0U1ojUtVz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDA0NiBTYWx0ZWRfXwXRoskbbk0XJ N0hSxpZDNZXtPVygc/CK7GEfYbJYqjJJwny2V3XZLNexQabWhKXXhnQzjxBjwTpY7urOKyR4+Qv 8eZAB+7c2Kc2OnaqUHeZMaVpsTkZKgPXd6vJBoTkE36gN8bgsBVwWsrdVUKzG+KIDJsXejvmxHD wxm4YuLt6L6RDu0i8j1P6/VpPSMTpFcTa70vcGJz57iDLWg0a9bXuS2o4zVkw34KWWOyGwjF3j3 v36hY7jkPPQSeUtve9CAv4uTK0IrLhRqoOM3VEnzJzgfAFT+k5sKay1Lewwnl/N8i8cW0fW9S1S wlQFc/IWH3Lq9cYHMY3PqstmW2dzckyYb8WaKTijKhIdmUya0eQ7qOSamBzIzfEP+2mh1bbOAxM KmNYIBgmJUYZXpY2O47nZ5EOoU4uOcvegt+7xtBZbOu5PxW5W6bVzk7QnceCnZ+vevYHRNLuFGD wq5dlhBWh7BSgjVtsdw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_01,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200046 On 5/12/2026 4:58 PM, Konrad Dybcio wrote: > On 5/5/26 2:23 PM, Umang Chheda wrote: >> Add AEST RAS error source nodes for the Monaco SoC. >> >> The DT describes a processor error source covering all CPU cores and a >> shared L3 cache error source for the cluster. These nodes model the >> hardware error reporting blocks and associated interrupts as required >> by the Arm AEST specification. >> >> Co-developed-by: Faruque Ansari >> Signed-off-by: Faruque Ansari >> Signed-off-by: Umang Chheda >> --- >> arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi >> index 7b1d57460f1e..8e43ceed7d84 100644 >> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi >> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi >> @@ -3,6 +3,7 @@ >> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> +#include >> #include >> #include >> #include >> @@ -29,6 +30,46 @@ / { >> #address-cells = <2>; >> #size-cells = <2>; >> >> + aest { >> + compatible = "arm,aest"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; > > These 3 properties aren't necessary if none of the subnodes have a > 'reg' property Ack > > Konrad Thanks, Umang