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Wed, 23 Sep 2026 13:12:10 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 23 Sep 2026 13:12:09 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , , Shuai Xue Subject: [PATCH v6 14/17] iommu/arm-smmu-v3: Add has_ats to struct arm_smmu_cmdq_batch Date: Wed, 23 Sep 2026 13:11:33 -0700 Message-ID: <5560b3d2aff6f2cb3839f6cb854a1ed27b2dfb69.1790188511.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E63:EE_|DM4PR12MB7768:EE_ X-MS-Office365-Filtering-Correlation-Id: 289d661c-62c3-4f2d-9b0b-08df19af0176 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|23010399003|36860700016|10067099003|11063799006|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: FhTgisNim96Wwy3J2Ie/2ZLl3xHeAkaye/jET10n/VCHOvG+TMlY7d0u1s7pHlfulRvqQCe5lsy1CVLm3KHcSXYVILRmjmQA5BrNQBr/mXqu05UcAVBxv3fIGBlMFU1m1yWGNo7mWsU4/qnF+KQDUcQzlo1l3ypey0VQyxqAOvItvUHM9FWRAYEv6UwQvuQ/YbBXeKNhBsWt5VnE53r3BUT3rnaqcN3lorfyLyhVr+WQ/c1zLnKSiVIFOxEkxvoHTQoTBzjTgLGPyC9oowEzATBTZj0xZnayHq1sGsPqAFaCBvSqfbVoBSE33VFasQ2bT3IQt6nZuoamvmMW+0XRueuk3kvoYeVTj8G+Hm8Z3NaRfhEVGtOgq+Cmnq3DYLI5a1wj1+aI4R8Q+Fwa7MBM5Rh1rhBGpnyZMNBza9cs++nT4FT2L6SGEhp64UcRa1fdu8zVvniWmfmuXpGxY2XJF+anF63knyS71xZcqXlUr52y1Dkxffv6i3r0DPvHntSu4wvwE9TbFiVNWZnOFxJVQc+6kN2xB/VDqBs7nStujA0JSQEP0VYjTfoA9CEc++rNqwdGJhoVj+QXHsHDpXBK7mJHLbWFoZkV7ATPd6cjNYHZqYqLBXwB025ohWd88ZnDmkevxGP4mP71VMdZ0J4T4oQOvI8OzPklvPWjEr+l+b2kih05dgZuv/fVBIxfXNHKxJK1YIlN320VPN3prGapWA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(23010399003)(36860700016)(10067099003)(11063799006)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Xezt9ctYAPfP/eXpMf4on6F8BKg9dYcEx7z+oB82Vs6tz5Bplep6L9CUBIQLsIVnqLc2YkvR+ItwuB2cTnlXO/1fIES8VFA84pk5jY6ww+oDNfru4RN0zYYivp8co7F+3LIBltkewey6HrjwZhM9mC4LadauhM58xG3D4n8iO0n93bfgHKvRIe3dp5J86YFLClXtKQF19mtf/cdXBsQ2xelgfzFlPGFOQ6csFL+rqqrqdX/H6TeVhY5pFxPp1nnkYbvRzxnEnSYuNhYVcjRDHrf80TKTAH+rHf1Y7h2xN6pAuhE9zCxyg0pZvu8Q6MZNfOfesF378QpvYCCXjJqphzULn3xSsVsMvaPZwu8V8ZiEZ635YR1c6Cn+qKUkiewcmmILzMNG5NeS8J78JnvQ9NearOFQdhP5rczRbIlDBSQ3cMz2Ka9HwG4U0c9BjGo+ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 20:12:34.3489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 289d661c-62c3-4f2d-9b0b-08df19af0176 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E63.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7768 The arm_smmu_cmdq_batch_add_cmd_p() might flush a sub-batch mid-way, when the ARM_SMMU_OPT_CMDQ_FORCE_SYNC is set or when a batch is full. To allow a future change to retry these sub-batch flushes on a timeout and identify the broken master, the batch needs to know whether it holds an ATC_INV. Add a "has_ats" flag, set by arm_smmu_cmdq_batch_add_cmd_p() when it queues an ATC_INV command. No functional changes. Assisted-by: LLM Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 2f8d22cc404ac..6fa4f390ad133 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -724,6 +724,8 @@ static inline bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq, struct arm_smmu_cmdq_batch { struct arm_smmu_cmd cmds[CMDQ_BATCH_ENTRIES]; struct arm_smmu_cmdq *cmdq; + /* Set when an ATC_INV is queued; gates the retry-aware sync decision */ + bool has_ats; int num; }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6f217e916ab0c..607246a965a91 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -963,6 +963,7 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu, { cmds->num = 0; cmds->cmdq = arm_smmu_get_cmdq(smmu, cmd); + cmds->has_ats = false; } static int arm_smmu_cmdq_batch_issue(struct arm_smmu_device *smmu, @@ -1011,6 +1012,8 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); } + if (FIELD_GET(CMDQ_0_OP, cmd->data[0]) == CMDQ_OP_ATC_INV) + cmds->has_ats = true; cmds->cmds[cmds->num++] = *cmd; } -- 2.43.0