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From: Krzysztof Kozlowski <krzk@kernel.org>
To: "Nazle Asmade,
	Muhammad Nazim Amirul"
	<muhammad.nazim.amirul.nazle.asmade@altera.com>,
	"dinguyen@kernel.org" <dinguyen@kernel.org>
Cc: "robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees
Date: Thu, 4 Jun 2026 13:15:08 +0200	[thread overview]
Message-ID: <62e4809b-078b-432f-a3b1-59559a4aa77f@kernel.org> (raw)
In-Reply-To: <47a7cb44-416b-4e48-a7f2-b6b69b71896a@altera.com>

On 04/06/2026 12:55, Nazle Asmade, Muhammad Nazim Amirul wrote:
> On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote:
>> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>>
>>> Enable the SMMU on the SoCFPGA board device trees where it was
>>> missing. The SoC uses a different memory-mapped base address for
>>> its peripherals, which requires the System Memory Management Unit
>>> (SMMU) to be active so that the Secure Device Manager (SDM) can
>>> correctly access those regions through address translation.
>>>
>>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>> ---
>>> Changes in v2:
>>> - Move SMMU enable into the base DTSI file instead of individual DTS files
>>>
>>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> index b06c6d5d60ee..64f3739a0c33 100644
>>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>>>                        interrupt-names = "eventq", "gerror", "priq";
>>>                        dma-coherent;
>>>                        #iommu-cells = <1>;
>>> -                     status = "disabled";
>>> +                     status = "okay";
>>
>> Which file disabled it?
>>
>> Best regards,
>> Krzysztof
> Hi Dinh, Krzysztof
> 
> Thank you for the review and feedback!
> 
> Addressing Dinh's comment — the commit header has been updated to follow 
> the subsystem naming convention.
> 
> Addressing Krzysztof's question — the SMMU was disabled in 
> socfpga_agilex5.dtsi itself, where the node is defined with status = 
> "disabled". This has been clarified in the updated commit message.

This makes no sense. I am asking which nod makes it disabled now, that
you need to enable it.

Best regards,
Krzysztof

  reply	other threads:[~2026-06-04 11:15 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-15  8:00 [PATCH v2 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC muhammad.nazim.amirul.nazle.asmade
2026-05-15  8:00 ` [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees muhammad.nazim.amirul.nazle.asmade
2026-05-15 11:51   ` Dinh Nguyen
2026-05-30 11:11   ` Krzysztof Kozlowski
2026-06-04 10:55     ` Nazle Asmade, Muhammad Nazim Amirul
2026-06-04 11:15       ` Krzysztof Kozlowski [this message]
2026-06-04 12:00         ` Nazle Asmade, Muhammad Nazim Amirul
2026-06-04 12:42           ` Krzysztof Kozlowski
2026-06-05  2:31             ` Nazle Asmade, Muhammad Nazim Amirul
2026-05-15  8:00 ` [PATCH v2 2/2] arm64: dts: socfpga: Add dma-coherent to XGMAC nodes muhammad.nazim.amirul.nazle.asmade
2026-05-15 11:52   ` Dinh Nguyen

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