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Wed, 07 Oct 2026 00:33:49 -0700 (PDT) X-Received: by 2002:a17:90a:e704:b0:3a8:d1c:8e67 with SMTP id 98e67ed59e1d1-3a8a0e097f0mr1239245a91.35.1791358429295; Wed, 07 Oct 2026 00:33:49 -0700 (PDT) Received: from [10.204.78.119] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a851630206sm8776843a91.0.2026.10.07.00.33.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 00:33:45 -0700 (PDT) Message-ID: <896dc089-b3be-4bad-872a-906deaa97071@oss.qualcomm.com> Date: Wed, 7 Oct 2026 13:03:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/17] phy: qcom: edp: Add Nord PLL configuration callback To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Kuogee Hsieh , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Ritesh Kumar , Mahadevan P References: <20260911-nord-drv-dt-v1-0-e25c073cf1b6@oss.qualcomm.com> <20260911-nord-drv-dt-v1-14-e25c073cf1b6@oss.qualcomm.com> Content-Language: en-GB From: Nabige Aala In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: SzoOWMHeIC--5HQI_PXHVbTaRU4lDmAO X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAyOCBTYWx0ZWRfX2C8ZGtM/DBUS qfYJHwxblShrEESBioH50i1CD4he7XLogCVJZxe0y3Dh6tzAzaFKFcTQSoNpPKQ7G4PGEgbO7Jm meDOgNrgb2kpc4DmCjYl6J7kruMeQRk= X-Authority-Analysis: v=2.4 cv=PM+aavqC c=1 sm=1 tr=0 ts=6ac5f5de cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=UbSN2h5EAu2IQE0OKKEA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: SzoOWMHeIC--5HQI_PXHVbTaRU4lDmAO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAyOCBTYWx0ZWRfX1EWRnlnByisI YMc2TTz0v1HuZNBOLi6Ek0bHlI+0wma31lSlZYs4nFULXJXn/CE4WohvBzB0ZQw71YlBfdeGBSG jd4qj7Ehx2/ZbnBizkwj9gfxrw3AdnEsrR/DpFsygPUNr9+1w5x2MbS+/bkI211khiHQp1fJaNW LfRSFB5TqmJOllvo4JN+Y4p0kaq680cZqFxjYPdKHIWOxQxYIiS5PHGMd+f2LAJWrL46UgrkSAp SebX592Ozfm9F1OeMyHPxwFhithIAn6VKNVwRkr6Rgvj+BNCg7fDtyo0uMG/iM3SagW7tFjmrFE 0L3IzHS9zD4FQD/3QmrfbpMAU/0/B34tIUp8ut871IZlxvHIbjunJCGcIwCBWCXBDjbF3l8n1PB vb5MYvLX2JFfgVkyLFHwfMAkpjxrDSzOezcBaO9oMliW967v0H/a/kxdnfO7AAWCwvBPa4x04tW eG2hf71mBAXPsgx4GBA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_02,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070028 On 9/14/2026 5:42 AM, Dmitry Baryshkov wrote: > On Fri, Sep 11, 2026 at 09:06:45PM +0530, Nabige Aala wrote: >> From: Ritesh Kumar >> >> Nord uses a 38.4 MHz CXO reference with a different QSERDES v8 COM >> register layout and PLL coefficients. Add >> qcom_edp_com_configure_pll_nord() which programs all QSERDES COM PLL >> registers with link-rate-dependent values for RBR, HBR, HBR2 and >> HBR3, per HPG Table 2-1-d. >> >> Signed-off-by: Ritesh Kumar >> Signed-off-by: Nabige Aala >> --- >> drivers/phy/qualcomm/phy-qcom-edp.c | 112 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 112 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c >> index a0f4b12e561e..4d1b2c81d956 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-edp.c >> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c >> @@ -1688,6 +1688,118 @@ static int qcom_edp_com_configure_ssc_nord(const struct qcom_edp *edp) >> } >> >> >> +/* >> + * Nord PLL configuration per HPG Table 2-1-d, CXO = 38.4 MHz. >> + * Supported link rates: 1.62 Gbps (RBR), 2.7 Gbps (HBR), >> + * 5.4 Gbps (HBR2), 8.1 Gbps (HBR3). >> + */ >> +static int qcom_edp_com_configure_pll_nord(const struct qcom_edp *edp) >> +{ >> + const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; >> + u32 div_frac_start1_mode0; >> + u32 div_frac_start2_mode0; >> + u32 div_frac_start3_mode0; >> + u32 dec_start_mode0; >> + u32 lock_cmp1_mode0; >> + u32 lock_cmp2_mode0; >> + u32 lock_cmp_en; >> + u32 hsclk_sel; >> + u32 code1_mode0; >> + u32 code2_mode0; >> + u32 core_clk_div_mode0 = 0x14; >> + >> + switch (dp_opts->link_rate) { >> + case 1620: >> + hsclk_sel = 0x0c; >> + dec_start_mode0 = 0x54; >> + div_frac_start1_mode0 = 0x00; >> + div_frac_start2_mode0 = 0x00; >> + div_frac_start3_mode0 = 0x06; >> + lock_cmp1_mode0 = 0x37; >> + lock_cmp2_mode0 = 0x04; >> + lock_cmp_en = 0x04; >> + code1_mode0 = 0x8d; >> + code2_mode0 = 0x27; > No extra alignment, please. Ack > >> + break; >> + >> + case 2700: >> + hsclk_sel = 0x04; >> + dec_start_mode0 = 0x46; >> + div_frac_start1_mode0 = 0x00; >> + div_frac_start2_mode0 = 0x00; >> + div_frac_start3_mode0 = 0x05; >> + lock_cmp1_mode0 = 0x07; >> + lock_cmp2_mode0 = 0x07; >> + lock_cmp_en = 0x08; >> + code1_mode0 = 0xf6; >> + code2_mode0 = 0x20; >> + break; >> + >> + case 5400: >> + hsclk_sel = 0x01; >> + dec_start_mode0 = 0x46; >> + div_frac_start1_mode0 = 0x00; >> + div_frac_start2_mode0 = 0x00; >> + div_frac_start3_mode0 = 0x05; >> + lock_cmp1_mode0 = 0x0f; >> + lock_cmp2_mode0 = 0x0e; >> + lock_cmp_en = 0x08; >> + code1_mode0 = 0xf6; >> + code2_mode0 = 0x20; >> + break; >> + >> + case 8100: >> + hsclk_sel = 0x03; >> + dec_start_mode0 = 0x4f; >> + div_frac_start1_mode0 = 0x00; >> + div_frac_start2_mode0 = 0xa0; >> + div_frac_start3_mode0 = 0x01; >> + lock_cmp1_mode0 = 0x17; >> + lock_cmp2_mode0 = 0x15; >> + lock_cmp_en = 0x08; >> + code1_mode0 = 0x14; >> + code2_mode0 = 0x25; >> + core_clk_div_mode0 = 0x0a; >> + break; >> + >> + default: >> + return -EINVAL; >> + } >> + >> + writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL_NORD); >> + writel(0x0b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL); >> + writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL); >> + writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1); >> + writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE); >> + writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT); >> + writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1); >> + writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO); >> + writel(lock_cmp_en, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN); >> + writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0); >> + writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0); >> + writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0); >> + writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0); >> + writel(div_frac_start1_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0); > Always 0x00 Ack, This value is always 0x00 will update this in next revision. > >> + writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0); >> + writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0); >> + writel(0x12, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1); >> + writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0); >> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0); >> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP); >> + writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0); >> + writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0); >> + writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER); >> + writel(core_clk_div_mode0, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0); >> + writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL); >> + writel(0x1d, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); > Not 0x1f? Ack, This should be 0x1f. I will update in next revision. > >> + writel(0x0f, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN); > No DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 / > DP_QSERDES_V8_COM_VCO_TUNE2_MODE0? As per HPG, We dont need to programmed these for Nord. Thanks, Nabige >> + writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0); >> + writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0); >> + >> + return 0; >> +} >> + >> + >> static const struct of_device_id qcom_edp_phy_match_table[] = { >> { .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, }, >> { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, }, >> >> -- >> 2.34.1 >>