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[209.85.217.44]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5cc65296997sm2390353e0c.13.2026.09.25.05.58.08 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Sep 2026 05:58:08 -0700 (PDT) Received: by mail-vs1-f44.google.com with SMTP id ada2fe7eead31-78a338fe106so1643393137.0 for ; Fri, 25 Sep 2026 05:58:08 -0700 (PDT) X-Forwarded-Encrypted: i=1; AKwUvBwnmdI1Lotk7S9zcOUdvXJ58sJISF4FcGn9zLYS119YQ5y/13wHAZppTEAda5zItNc2niNe5Rgw+EFj+vk=@vger.kernel.org X-Received: by 2002:a05:6102:a145:b0:78f:fee6:832 with SMTP id ada2fe7eead31-7af1cea4a54mr1503499137.12.1790341087879; Fri, 25 Sep 2026 05:58:07 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260924-paul-v7-3-rc1-edac-v3-0-bd8054a5b180@bootlin.com> <20260924-paul-v7-3-rc1-edac-v3-1-bd8054a5b180@bootlin.com> <8733uxlcl1.fsf@bootlin.com> In-Reply-To: <8733uxlcl1.fsf@bootlin.com> From: Geert Uytterhoeven Date: Fri, 25 Sep 2026 14:57:56 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AclHuK-YV8P6qGPlYAimFvYOFx6QV9kkt9w-v-Qt2g3Qun14B0iXjB41Jl3A5uU Message-ID: Subject: Re: [PATCH v3 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC binding To: Miquel Raynal Cc: Wolfram Sang , Paul Louvel , Borislav Petkov , Tony Luck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-edac@vger.kernel.org, devicetree@vger.kernel.org, Thomas Petazzoni , Herve Codina Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Miqu=C3=A8l, On Fri, 25 Sept 2026 at 14:50, Miquel Raynal wr= ote: > > But one thing came to my attention just now which needs fixing: > > > >> + items: > >> + - const: renesas,r9a06g032-ddr-edac # RZ/N1D > >> + - const: renesas,rzn1-ddr-edac # RZ/N1 > > > > We don't need a family compatible. Only N1D has a DDR controller. > > This is true, but from my experience with this platform, Geert used to > request both. I'm fine exposing only one of them, but I explicitly asked > Paul to put them both to mimic the existing bindings and keep some kind > of uniformity. I'm fine either ways, but before we go through that > iteration, Geert, would you mind confirming your preferences? Well, if only RZ/N1D has the DDR controller, there is not much point in adding a family-specific compatible value. According to renesas.com, RZ/N1x is obsolete, so no new family members will arrive. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds