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list To: Andrew Jones , linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> <20260925151659.419512-11-andrew.jones@oss.qualcomm.com> Content-Language: en-US From: "Nutty.Liu" In-Reply-To: <20260925151659.419512-11-andrew.jones@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TPYP295CA0024.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:a::13) To SE3PR04MB8922.apcprd04.prod.outlook.com (2603:1096:101:2e9::7) X-Microsoft-Original-Message-ID: <4b40670e-280c-4caa-b474-3ffc673cd115@hotmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: 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=?utf-8?B?OWlPV2ZIVENpN2NMZ2lidEI3ejhmL0UrNTBFSmNVSDJhcTRWWngrZFdYTFM4?= =?utf-8?Q?jIdk9YziZX/TB?= X-OriginatorOrg: sct-15-20-9412-4-msonline-outlook-c3e7a.templateTenant X-MS-Exchange-CrossTenant-Network-Message-Id: 1caf01d9-0895-4fe7-c48c-08df1d10627d X-MS-Exchange-CrossTenant-AuthSource: SE3PR04MB8922.apcprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 03:27:12.2481 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR04MB7100 On 9/25/2026 11:16 PM, Andrew Jones wrote: > Upcoming RISC-V IOMMU interrupt remapping needs to map every possible > host IMSIC target into one contiguous MSI IOVA range. MSI message > composition then uses the target CPU's position within that range. > > Build an IMSIC physical address array indexed by logical CPU. > Require every possible CPU to have an initialized IMSIC page before > publishing the array. This preserves physical address zero as a valid > target and guarantees the array has num_possible_cpus() entries. > > The array size and each target's index can therefore be derived > directly, without storing duplicate count or per-CPU index metadata. > > Signed-off-by: Andrew Jones > Tested-by: Fangyu Yu Reviewed-by: Nutty Liu Thanks, Nutty > --- > drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++++++++++++++++++ > drivers/irqchip/irq-riscv-imsic-state.h | 3 +++ > 2 files changed, 35 insertions(+) > > diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c > index df38a7670a89..abd1cdb640ea 100644 > --- a/drivers/irqchip/irq-riscv-imsic-state.c > +++ b/drivers/irqchip/irq-riscv-imsic-state.c > @@ -709,6 +709,31 @@ static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, > return of_address_to_resource(to_of_node(fwnode), index, res); > } > > +static int __init imsic_init_msi_pa_list(void) > +{ > + struct imsic_global_config *global = &imsic->global; > + phys_addr_t *msi_pa_list; > + unsigned int cpu; > + > + msi_pa_list = kcalloc(num_possible_cpus(), sizeof(*msi_pa_list), GFP_KERNEL); > + if (!msi_pa_list) > + return -ENOMEM; > + > + for_each_possible_cpu(cpu) { > + struct imsic_local_config *local = per_cpu_ptr(global->local, cpu); > + > + if (!local->msi_va) { > + kfree(msi_pa_list); > + return -ENODEV; > + } > + > + msi_pa_list[cpu] = local->msi_pa; > + } > + > + imsic->msi_pa_list = msi_pa_list; > + return 0; > +} > + > static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, > struct imsic_global_config *global, > u32 *nr_parent_irqs, > @@ -959,6 +984,12 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) > goto out_local_cleanup; > } > > + rc = imsic_init_msi_pa_list(); > + if (rc) { > + pr_err("%pfwP: failed to initialize MSI address list\n", fwnode); > + goto out_local_cleanup; > + } > + > /* Initialize matrix allocator */ > rc = imsic_matrix_init(); > if (rc) { > @@ -984,6 +1015,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) > out_free_local: > free_percpu(imsic->global.local); > out_free_priv: > + kfree(imsic->msi_pa_list); > kfree(imsic); > imsic = NULL; > return rc; > diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h > index c42ee180b305..e51c61dcced3 100644 > --- a/drivers/irqchip/irq-riscv-imsic-state.h > +++ b/drivers/irqchip/irq-riscv-imsic-state.h > @@ -50,6 +50,9 @@ struct imsic_priv { > /* Global configuration common for all HARTs */ > struct imsic_global_config global; > > + /* MSI target physical addresses indexed by logical CPU for IOMMU mapping */ > + phys_addr_t *msi_pa_list; > + > /* Per-CPU state */ > struct imsic_local_priv __percpu *lpriv; >