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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5329292a-8fa2-4604-83af-08df0caa6cf6 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2026 06:37:02.1550 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: t/CQwz67JhMJMUWMPGJyrbsm4G5MAwOk3YBL+T9QY5xFYymc4Itc38WGqWqojKNbd+tnpLPfbO/K9R21WoTNrO0EJZpczyoPGGbmuHGJ0pg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY3PR01MB10353 Hi Wolfram, Thanks for the feedback. > -----Original Message----- > From: Wolfram Sang > Sent: 03 September 2026 10:38 > Subject: Re: [PATCH v24 08/15] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_D= IVIDER flag >=20 > > Thank you for your contribution! Sashiko AI review found 1 potential is= sue(s) to consider: > > - [Medium] Fallback `f_max` and `f_min` initialization fails to account= for the internal clock divider. > > -- > > > > --- Patch [8]: [PATCH v24 08/15] mmc: renesas_sdhi: Add > > TMIO_MMC_INTERNAL_DIVIDER flag --- commit > > c4a63c19303286f5b383bdabaa2a3f3827a8c5c5 > > Author: Biju Das > > > > mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag > > > > This commit introduces the TMIO_MMC_INTERNAL_DIVIDER flag to support > > SoCs like RZ/G3L that have a fixed internal /2 clock divider. It adds > > a helper function to fold this division into the reported clock rate > > and uses it in the clock update path. > > > > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c > > > b/drivers/mmc/host/renesas_sdhi_core.c > > > index ff428b6187bbd..b5f2ff68db758 100644 > > > --- a/drivers/mmc/host/renesas_sdhi_core.c > > > +++ b/drivers/mmc/host/renesas_sdhi_core.c > > > @@ -125,6 +125,27 @@ static int renesas_sdhi_clk_enable(struct tmio_m= mc_host *host) > > > return 0; > > > } > > > > > > > [Severity: Medium] > > Since this patch introduces an internal /2 clock divider, should > > renesas_sdhi_clk_enable() (which is just above this hunk) also be > > updated to account for it? For this patch, we don't have a SoC with TMIO_MMC_INTERNAL_DIVIDER flag set= . So, it retains previous functionality. Please comment if you think otherwis= e. > > > > If the device tree omits the max-frequency property, f_max defaults to > > the raw parent clock rate: > > This behaviour is same as there is no SoC has set with TMIO_MMC_INTERNAL_DI= VIDER flag. > > drivers/mmc/host/renesas_sdhi_core.c:renesas_sdhi_clk_enable() { > > ... > > if (!mmc->f_max) > > mmc->f_max =3D clk_get_rate(priv->clk); The SoC with TMIO_MMC_INTERNAL_DIVIDER has always frequency defined in SoC = dtsi and this condition is skipped. Please let me know should I add a comment he= re?? > > > > /* > > * Minimum frequency is the minimum input clock frequency > > * divided by our maximum divider. > > */ > > mmc->f_min =3D max(clk_round_rate(priv->clk, 1) / host->pdata->max_div= ider, 1L); > > ... > > } > > > > For hardware with the internal divider, this advertises double the > > actual achievable bus frequency. If the clock provider cannot scale up > > to 4x the requested frequency, the MMC core might negotiate a > > high-speed mode that the hardware cannot satisfy, resulting in a mode > > mismatch where the bus silently runs at half the expected speed. SDx_Clock (HS clk) Figure 4.4-8 Block Diagram of the Deformed Clock System = (7) IMCLK =3D SDx_Clock/2 SD_Clock Figure 6.2-2 Functional Diagram of Clock Divider for SD_CLK SD_Clock is dynamic setting based on the speed mode. For HS400 mode, SD_CLK =3D IMCLK =3D SDx_Clock/2 and SD_CLK_CTRL =3D 0 For Non-HS400 mode, SD_CLK =3D IMCLK /2 =3D SDx_Clock/4 and SD_CLK_CTRL =3D= 0xff for 1/1 option and other values for non 1/1 option. We know the maximum frequency supported by the SoC and we must define this = in SoC dtsi. I believe we should support the below check only for non-DT platforms as we= don't know the SoC max sd clock capability. if (!mmc->f_max) mmc->f_max =3D clk_get_rate(priv->clk); > > > > Could mmc->f_max and mmc->f_min calculation be adjusted when the > > TMIO_MMC_INTERNAL_DIVIDER flag is set? >=20 > Looks valid from a glimpse. Please comment if you think this report makes= sense or not. Please comment on my response. Cheers, Biju