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Fri, 25 Sep 2026 06:30:14 +0000 From: Changhuang Liang To: Mark Brown CC: Serge Semin , "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v1 1/2] spi: dw: Request DMA channels at runtime instead of probe Thread-Topic: [PATCH v1 1/2] spi: dw: Request DMA channels at runtime instead of probe Thread-Index: AQHdS0HoNlKEArO3nEamu3mxZh2zNbbeBy+AgADQ8SA= Date: Fri, 25 Sep 2026 06:30:14 +0000 Message-ID: References: <20260923095705.233297-1-changhuang.liang@starfivetech.com> <20260923095705.233297-2-changhuang.liang@starfivetech.com> <4688e732-0fab-4e23-9d3c-e0326b3bd65e@sirena.org.uk> In-Reply-To: <4688e732-0fab-4e23-9d3c-e0326b3bd65e@sirena.org.uk> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1332:EE_ x-ms-office365-filtering-correlation-id: 0b0e657b-0baa-4157-0707-08df1ace755a x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0;ARA:13230040|376014|1800799024|366016|23010399003|10067099003|56012099006|4143699003|38070700021|22082099003|18002099003; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-Network-Message-Id: 0b0e657b-0baa-4157-0707-08df1ace755a X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Sep 2026 06:30:14.4082 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ma1O40zw80Kb7M1nEZw03iRp2ulRqPL3VkaqIoQ6UyLZfBnKfZZEL8cdr4TZgL6qePA8FtcM1xSRxBFE4KMf2R296X5cFi/mpqrZSaRwodJZBEGc0mCNsP6R0NH39XFZ X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ4PR01MB1332 Hi, Mark Thanks for the review. > On Wed, Sep 23, 2026 at 02:57:04AM -0700, Changhuang Liang wrote: > > The DW SPI controller requests its DMA channels in > > dw_spi_add_controller(), which ties them up for the entire lifetime of > > the controller. Even a controller that is only ever used for standard > > SPI transfers and never for enhanced SPI transfers holds the channels > > exclusively from probe onwards, preventing them from being shared with > > other users. >=20 > > +static int dw_spi_prepare_hardware(struct spi_controller *ctlr) { > > + struct dw_spi *dws =3D spi_controller_get_devdata(ctlr); > > + int ret; > > + > > + if (!ctlr->can_dma) > > + return 0; > > + > > + ret =3D dws->dma_ops->dma_init(ctlr->dev.parent, dws); > > + if (ret) { > > + /* > > + * DMA is optional: fall back to the PIO/IRQ path instead of > > + * failing the message. Use dev_dbg() since this may happen > > + * on every prepare. > > + */ > > + dev_dbg(&ctlr->dev, "DMA init failed (%d), using PIO\n", ret); > > + > > + return 0; > > + } > > + > > + return 0; > > +} >=20 > This seems like a lot of overhead for every existing controller with DMA,= we'll > have to go through the request/release cycle whenever DMA gets used which > feels like a bunch of overhead for a hot path - especially in the fast pa= th in > spi_sync(). If some platforms need it they should be able to opt into it= rather > than forcing it on every single platform. >=20 I will reorganize this series, trying to avoid affecting the current flow. > > +static int dw_spi_unprepare_hardware(struct spi_controller *ctlr) { >=20 > Adding this also causes overhead since we do the unprepare in the thread. Best Regards, Changhuang