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Wed, 23 Sep 2026 13:11:52 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , , Shuai Xue Subject: [PATCH v6 02/17] PCI/CXL: Probe the underlying bus reset in cxl_reset_bus_function() Date: Wed, 23 Sep 2026 13:11:21 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E64:EE_|LV5PR12MB9756:EE_ X-MS-Office365-Filtering-Correlation-Id: 95044287-51ab-4ea6-a223-08df19aefa18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|7416014|376014|82310400026|1800799024|18002099003|22082099003|56012099006|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: r4kQjJUfcwdcvApxlrCvdgaAhdbVSy5Y4a/PPyHGSFTL7vNmt1s0BFl31H6dHw7pVHDecsUSUgBvQWXH9rObCZGiITQrLeHYvoAnBKZecRTieJFz9b4cNNXzTVOyeW/GnDPhuee7sx3QStqVZrkH5qAE0khN5ealVxupDmg87JgKIRYO/ikq8WUjonMZRZLPxUlSip3WrS+6kgIbA5MQFV6dnUAon9lLA5qrqqiX1Wkggah2aGetm3F//YbHKToD//aujhBfjrrYWqAI4Zx1Y0zXA3V4cHFHMDzsTXpOUNIFIDu7Um68rzy0ShoW+yPk8eq3HIyLzQ8H4UEz3xIgdUv1eCiNEQwFPXob6M2Hl9pepZjLz1nexd1SDtx2UU+fIZjBMuyUDcYEmKk9+ndLPzh/sXH8wBsnT0YWEMJMhBpU2+gdlN34V0wiaGjjCUpUm8lr7zwJKEmn5YOorUErTHOuwe1KH1ZJEttrf1SSYb2CR7fjidHFmcqPnB+p9PP7vVmz1uKus8xGdPAfHY77UkyM9Fl4za/UZcKXd6AjMsKEQWdnAUjefTF8OFdOGV9G6rDfvIy3HZRpTfDD6RtL8s2tObo1an6RrCSxTUDFkz4WolC7U/UIEZAIq4EWX0rOVVib74E3zUhKzMiv/79iTIe78la3K6nVh2oDl/BZmVmmckKbcf4fWPVDBRNEJDhd X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(7416014)(376014)(82310400026)(1800799024)(18002099003)(22082099003)(56012099006)(11063799006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DSZJO0cEFib6zJkz2Xsosiga6+6Bzq6K/8u3nyxt2gXeXYpkoHS7bMz600r55kznc7gdUWo4EQ7bLDSNBHvpynulf/1e/O41Oym4tJFiefnZo7uQWhNDRQOLcvz209117V0HQpMwJp7Pzd+JKT0587JTY9BLeUu1gvdVB6IgoRZ0YpANbKuxDprPtQbnBQTR1cdjMH8wK2OObXQhQAqqPJwEwaxAOWjE/e49CI4HJ/B6PDny55yxC7KDncjCXGJ2n4LmnHkxJ+Z3360Vr/uWcd07ZZ4OPLIecn3wPxu2lNShyvmEmD/WWgsGUGxCpurj/WxaEhalscE5sr6VA0/pWspAwdG2uXpxmnJ2NSCNUjqRVJWzlpAOPmPQIHuwVTtIGjdWPLIUeYHgT2VcZ4VxAjdvilW+1lbqKdisQbIEW696oTEcn0kJIgfWpaj1f9JF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 20:12:21.9730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95044287-51ab-4ea6-a223-08df19aefa18 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E64.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9756 cxl_reset_bus_function() reports "supported" to a probe after checking only that the upstream bridge carries a CXL port DVSEC. The underlying bus reset can still be unavailable, e.g. on a bus shared with other devices, so both the reset_methods[] array and the reset_method sysfs node end up listing a "cxl_bus" that is guaranteed to fail with -ENOTTY when it is attempted. Probe the underlying pci_dev_reset_slot_function() and then, if it is not applicable, pci_parent_bus_reset(). These are the same two checks that the actual reset runs, so a shared-bus CXL device no longer advertises a method that can never succeed. Probing via pci_reset_bus_function() would not work: its cxl_sbr_masked() check rejects every CXL port with a masked SBR, while the do-reset path in this function unmasks the SBR before resetting. Such a port would wrongly probe as unsupported. Move the port control register read above the probe branch as well, so that probe runs the same checks. That read asserts no reset, and a failure means the device cannot be reset this way, which is a probe-time answer. Also pass an explicit PCI_RESET_DO_RESET at the do-reset call site, since probe is always false at that point. Fixes: 53c49b6e6dd2e ("PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports") Assisted-by: LLM Signed-off-by: Nicolin Chen --- drivers/pci/pci.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1eba412b7e0de..a6e0ecfd207a7 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5029,13 +5029,21 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) if (!dvsec) return -ENOTTY; - if (probe) - return 0; - rc = pci_read_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, ®); if (rc) return -ENOTTY; + /* + * Do not probe via pci_reset_bus_function(), which would reject a + * masked SBR that the do-reset path below unmasks before resetting. + */ + if (probe) { + rc = pci_dev_reset_slot_function(dev, PCI_RESET_PROBE); + if (rc != -ENOTTY) + return rc; + return pci_parent_bus_reset(dev, PCI_RESET_PROBE); + } + rc = pci_dev_reset_iommu_prepare(dev); if (rc) { pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc); @@ -5050,7 +5058,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) val); } - rc = pci_reset_bus_function(dev, probe); + rc = pci_reset_bus_function(dev, PCI_RESET_DO_RESET); if (reg != val) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, -- 2.43.0