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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Paul Burton <paulburton@kernel.org>,
	linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: Malta: Fix !EVA SOC-it PCI MMIO
Date: Tue, 11 Nov 2025 13:07:50 +0100	[thread overview]
Message-ID: <aRMnForYr_wNgbZ6@alpha.franken.de> (raw)
In-Reply-To: <alpine.DEB.2.21.2510191251130.39634@angie.orcam.me.uk>

On Mon, Oct 20, 2025 at 02:11:49AM +0100, Maciej W. Rozycki wrote:
> Fix a regression that has caused accesses to the PCI MMIO window to 
> complete unclaimed in non-EVA configurations with the SOC-it family of 
> system controllers, preventing PCI devices from working that use MMIO.
> 
> In the non-EVA case PHYS_OFFSET is set to 0, meaning that PCI_BAR0 is 
> set with an empty mask (and PCI_HEAD4 matches addresses starting from 0 
> accordingly).  Consequently all addresses are matched for incoming DMA 
> accesses from PCI.  This seems to confuse the system controller's logic 
> and outgoing bus cycles targeting the PCI MMIO window seem not to make 
> it to the intended devices.
> 
> This happens as well when a wider mask is used with PCI_BAR0, such as 
> 0x80000000 or 0xe0000000, that makes addresses match that overlap with 
> the PCI MMIO window, which starts at 0x10000000 in our configuration.
> 
> Set the mask in PCI_BAR0 to 0xf0000000 for non-EVA then, covering the 
> non-EVA maximum 256 MiB of RAM, which is what YAMON does and which used 
> to work correctly up to the offending commit.  Set PCI_P2SCMSKL to match 
> PCI_BAR0 as required by the system controller's specification, and match 
> PCI_P2SCMAPL to PCI_HEAD4 for identity mapping.
> 
> Verified with:
> 
> Core board type/revision =      0x0d (Core74K) / 0x01
> System controller/revision =    MIPS SOC-it 101 OCP / 1.3   SDR-FW-4:1
> Processor Company ID/options =  0x01 (MIPS Technologies, Inc.) / 0x1c
> Processor ID/revision =         0x97 (MIPS 74Kf) / 0x4c
> 
> for non-EVA and with:
> 
> Core board type/revision =      0x0c (CoreFPGA-5) / 0x00
> System controller/revision =    MIPS ROC-it2 / 0.0   FW-1:1 (CLK_unknown) GIC
> Processor Company ID/options =  0x01 (MIPS Technologies, Inc.) / 0x00
> Processor ID/revision =         0xa0 (MIPS interAptiv UP) / 0x20
> 
> for EVA/non-EVA, fixing:
> 
> defxx 0000:00:12.0: assign IRQ: got 10
> defxx: v1.12 2021/03/10  Lawrence V. Stefani and others
> 0000:00:12.0: Could not read adapter factory MAC address!
> 
> vs:
> 
> defxx 0000:00:12.0: assign IRQ: got 10
> defxx: v1.12 2021/03/10  Lawrence V. Stefani and others
> 0000:00:12.0: DEFPA at MMIO addr = 0x10142000, IRQ = 10, Hardware addr = 00-00-f8-xx-xx-xx
> 0000:00:12.0: registered as fddi0
> 
> for non-EVA and causing no change for EVA.
> 
> Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Fixes: 422dd256642b ("MIPS: Malta: Allow PCI devices DMA to lower 2GB physical")
> Cc: stable@vger.kernel.org # v4.9+
> ---
>  arch/mips/mti-malta/malta-init.c |   20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)

applied to mips-fixes

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

      reply	other threads:[~2025-11-11 12:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-20  1:11 Maciej W. Rozycki
2025-11-11 12:07 ` Thomas Bogendoerfer [this message]

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