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Wed, 3 Jun 2026 14:23:15 +0000 Date: Wed, 3 Jun 2026 16:23:04 +0200 From: Larysa Zaremba To: Jakub Raczynski CC: , , , , , , , , , , , Subject: Re: [PATCH net-next v2 2/3] net/stmmac/dwxgmac: Extend MTL/DMA support to 16 queues Message-ID: References: <20260601162537.553512-1-j.raczynski@samsung.com> <20260601162537.553512-3-j.raczynski@samsung.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260601162537.553512-3-j.raczynski@samsung.com> X-ClientProxiedBy: WA2PEPF000008AA.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d8::659) To SN7PR11MB7540.namprd11.prod.outlook.com (2603:10b6:806:340::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN7PR11MB7540:EE_|PH3PPFA3FE8A23F:EE_ X-MS-Office365-Filtering-Correlation-Id: 71ab822a-239f-4724-da60-08dec17ba663 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|10070799003|1800799024|366016|6133799003|56012099006|11063799006|4143699003|22082099003|18002099003; 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Before we increase max amount through macro, > prepare dwxgmac functions to handle that. Reviewed-by: Larysa Zaremba > > Co-developed-by: Chang-Sub Lee > Signed-off-by: Chang-Sub Lee > Signed-off-by: Jakub Raczynski > --- > .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++ > .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 23 +++++++++++++++++-- > 2 files changed, 23 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > index 51943705a2b0..bd333afe7e1b 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h > @@ -257,6 +257,8 @@ > #define XGMAC_MTL_INT_STATUS 0x00001020 > #define XGMAC_MTL_RXQ_DMA_MAP0 0x00001030 > #define XGMAC_MTL_RXQ_DMA_MAP1 0x00001034 > +#define XGMAC_MTL_RXQ_DMA_MAP2 0x00001038 > +#define XGMAC_MTL_RXQ_DMA_MAP3 0x0000103c > #define XGMAC_QxMDMACH(x) GENMASK((x) * 8 + 7, (x) * 8) > #define XGMAC_QxMDMACH_SHIFT(x) ((x) * 8) > #define XGMAC_QDDMACH BIT(7) > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > index dbedf31bb2ab..4aba62680938 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c > @@ -278,12 +278,31 @@ static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv *priv, > static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue, > u32 chan) > { > + struct net_device *ndev = hw->priv_data->dev; > void __iomem *ioaddr = hw->pcsr; > u32 value, reg; > > - reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; > - if (queue >= 4) > + switch (queue) { > + case 0 ... 3: > + reg = XGMAC_MTL_RXQ_DMA_MAP0; > + break; > + case 4 ... 7: > + reg = XGMAC_MTL_RXQ_DMA_MAP1; > queue -= 4; > + break; > + case 8 ... 11: > + reg = XGMAC_MTL_RXQ_DMA_MAP2; > + queue -= 8; > + break; > + case 12 ... 15: > + reg = XGMAC_MTL_RXQ_DMA_MAP3; > + queue -= 12; > + break; > + default: > + netdev_err(ndev, "%s: Incorrect queue mapping %d\n", > + __func__, queue); > + return; > + } > > value = readl(ioaddr + reg); > value &= ~XGMAC_QxMDMACH(queue); > -- > 2.34.1 > >