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Tue, 22 Sep 2026 12:45:22 -0700 Date: Tue, 22 Sep 2026 12:45:20 -0700 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , , , , Jason Gunthorpe Subject: Re: [PATCH v8 04/25] iommu/arm-smmu-v3: Move IDR parsing to common functions Message-ID: References: <20260922131259.2975334-1-smostafa@google.com> <20260922131259.2975334-5-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260922131259.2975334-5-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E5F:EE_|CH1PPF6B6BCC42C:EE_ X-MS-Office365-Filtering-Correlation-Id: 603dba0e-2a2e-49d8-1e87-08df18e21c7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700016|82310400026|23010399003|6133799003|3023799007|10067099003|56012099006|4143699003|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UgaSzjYVTYsa8G19ddVHwvFWzKm87VCJiWZizfOUXxstnyoMwvvcU9PFLFU86Hs3WRz813Y2avHti4K5Dv7WnNvH59NizUYe1f4yoXnl3mH7hQDHY/5uatF4jqIbbRo6gWPX/xn1qRy1BFSzmHHOYorXua1mVgJssAbpbRZ6EaeVzlTNxdsfTcbzZMdMcqmc8Rv/BlFpkAoJMbJGzJO7+pHJ+1g0umq5BVtzip6yOSgcxTa9FbuvEb4WT6k3VSSps9yBE/F7xp3b1YP8tHLN7VQ3XGTU8oIKgBQ4qqfR5JFBJ9NexAu1jcd4W9v/Dkjn+T+abwiwsATtvrFdMli2Egbl4W7bQwlbjmxsL8aqwrWInYPnlftILCJ0TTRzwl00pJ4W1UmEbbB/J9xFKkBUKHWKGDg0jD9VkuXhhglATg01vp7mCKrX02nvJkr6+EX4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2026 19:45:52.8128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 603dba0e-2a2e-49d8-1e87-08df18e21c7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E5F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF6B6BCC42C On Tue, Sep 22, 2026 at 01:12:37PM +0000, Mostafa Saleh wrote: > Move parsing of IDRs to functions so that it can be re-used > from the hypervisor. > > As the new functions operate on structs from both the hypervisor > and the kernel which would be different, we rely on the compilation > unit to having ARM_SMMU_OBJ point to the correct struct; some s/to having/to have > best-effort static asserts were added . s/added \./added\. > +#ifndef __ARM_SMMU_V3_COMMON_LIB_H > +#define __ARM_SMMU_V3_COMMON_LIB_H > + > +#include > +#include > +#include > + > +/* > + * The IDR probe functions are used by the kernel and the > + * hypervisor drivers where ARM_SMMU_OBJ might be defined > + * differently. > + * Ensure fields used by them are defined and has the correct > + * types. s/has/have We have 80 cols per line to write comments :) > + */ > +#ifndef __KVM_NVHE_HYPERVISOR__ > +typedef struct arm_smmu_device ARM_SMMU_OBJ; > +#endif It's probably safer to include arm-smmu-v3.h so everything would be self-defined. Also, Jason's suggestion in v7 was hyp_arm_smmu_v3_device, which looks nicer than ARM_SMMU_OBJ... > +static_assert(__same_type(typeof_member(ARM_SMMU_OBJ, features), u32)); > +static_assert(__same_type(typeof_member(ARM_SMMU_OBJ, options), u32)); > +static_assert(__same_type(typeof_member(ARM_SMMU_OBJ, oas), unsigned long)); > +static_assert(__same_type(typeof_member(ARM_SMMU_OBJ, pgsize_bitmap), unsigned long)); > +static_assert(__same_type(typeof_member(ARM_SMMU_OBJ, base), void __iomem *)); > + > +void arm_smmu_device_iidr_probe(ARM_SMMU_OBJ *smmu); > +u32 arm_smmu_idr0_probe(ARM_SMMU_OBJ *smmu); > +void arm_smmu_idr3_probe(ARM_SMMU_OBJ *smmu); > +u32 arm_smmu_idr5_probe(ARM_SMMU_OBJ *smmu); Can we use "arm_smmu_device_xyz_probe" matching with the existing arm_smmu_device_iidr_probe? > + if (coherent && !disable_msipolling && > + smmu->features & ARM_SMMU_FEAT_MSI) > + smmu->options |= ARM_SMMU_OPT_MSIPOLL; Will pKVM ever use MSIPOLL? > + if (smmu->features & ARM_SMMU_FEAT_HYP && > + cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) > + smmu->features |= ARM_SMMU_FEAT_E2H; Why is ARM64_HAS_VIRT_HOST_EXTN left behind? > - if (!(reg & (IDR0_S1P | IDR0_S2P))) { > + if (!(smmu->features & (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { > dev_err(smmu->dev, "no translation support!\n"); > return -ENXIO; This change seems unnecessary. The code above and below this line still uses "reg" returned by idr0_probe(). So, the original code should have read well: if (!!(reg & IDR0_COHACC) != coherent) dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", str_true_false(coherent)); if (!(reg & (IDR0_S1P | IDR0_S2P))) { dev_err(smmu->dev, "no translation support!\n"); return -ENXIO; } /* We only support the AArch64 table format at present */ if (!(FIELD_GET(IDR0_TTF, reg) & IDR0_TTF_AARCH64)) { dev_err(smmu->dev, "AArch64 table format not supported!\n"); return -ENXIO; } Nicolin